FDC2114 datasheet(13/61 Pages) TI1

13 / 61 page

fSENSOR3

(1)

÷ n

CH3_FREF_DIVIDER (0x17)

(1)

CH2_FREF_DIVIDER (0x16)

(1)

Int. Osc.

Core

tfREFt

Data Output

tfINTt

REF_CLK_SRC

(0x1A)

CONFIG (0x1A)

MUX_CONFIG

(0x1B)

÷ n

CH1_FREF_DIVIDER (0x15)

CH0_FREF_DIVIDER (0x14)

tfREF0t

tfREF1t

tfREF2

(1)t

tfREF3

(1)t

÷ m

CH3_FIN_SEL (0x17)

(1)

CH2_FIN_SEL (0x16)

(1)

tfINt

÷ m

CH1_FIN_SEL (0x15)

CH0_FIN_SEL (0x14)

tfIN0t

tfIN1t

tfIN2

(1)t

tfIN3

(1)t

tfCLKt

CONFIG (0x1A)

MUX_CONFIG

(0x1B)

IN2A

(1)

IN2B

(1)

IN3A

(1)

IN3B

(1)

IN1A

IN1B

IN0A

IN0B

fCLKIN

CLKIN

Cap

Sensor 3

(1)

fSENSOR2

(1)

Cap

Sensor 2

(1)

fSENSOR1

Cap

Sensor 1

fSENSOR0

Cap

Sensor 0

FDC2212, FDC2214, FDC2112, FDC2114

www.ti.com

SNOSCZ5A – JUNE 2015 – REVISED JUNE 2015

Feature Description (continued)

(1)

FDC2114 / FDC2214 only

Figure 12. Clocking Diagram

In Figure 12, the key clocks are fIN, fREF, and fCLK. fCLK is selected from either the internal clock source or external

clock source (CLKIN) . The frequency measurement reference clock, fREF, is derived from the fCLK source. It is

recommended that precision applications use an external master clock that offers the stability and accuracy

requirements needed for the application. The internal oscillator may be used in applications that require low cost

and do not require high precision. The fINx clock is derived from sensor frequency for a channel x, fSENSORx. fREFx

and fINx must meet the requirements listed in Table 1, depending on whether fCLK (master clock) is the internal or

external clock.

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