FDC2114 datasheet(12/61 Pages) TI1

12 / 61 page

IN0A

IN0B

IN3A

IN3B

FDC2114 / FDC2214

VDD

GND

SCL

SDA

Int. Osc.

ADDR

INTB

GND

MCU

VDD

3.3 V

GPIO

0.1 F 1 F

Core

peripheral

3.3 V

Cap

Sensor 0

CLKIN

40 MHz

Cap

Sensor 3

Resonant

circuit driver

Resonant

circuit driver

FDC2212, FDC2214, FDC2112, FDC2114

SNOSCZ5A – JUNE 2015 – REVISED JUNE 2015

www.ti.com

Functional Block Diagrams (continued)

Figure 11. Block Diagrams for the FDC2114 and FDC2214

The FDC is composed of front-end resonant circuit drivers, followed by a multiplexer that sequences through the

active channels, connecting them to the core that measures and digitizes the sensor frequency (fSENSOR). The

core uses a reference frequency (fREF) to measure the sensor frequency. fREF is derived from either an internal

reference clock (oscillator), or an externally supplied clock. The digitized output for each channel is proportional

to the ratio of fSENSOR/fREF. The I2C interface is used to support device configuration and to transmit the digitized

frequency values to a host processor. The FDC can be placed in shutdown mode, saving current, using the SD

pin. The INTB pin may be configured to notify the host of changes in system status.

9.3 Feature Description

9.3.1 Clocking Architecture

Figure 12 shows the clock dividers and multiplexers of the FDC.

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Product Folder Links: FDC2212 FDC2214 FDC2112 FDC2114

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