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DS90CF366, DS90CF386

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SNLS055J – NOVEMBER 1999 – REVISED MAY 2016

Product Folder Links: DS90CF366 DS90CF386

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Copyright © 1999–2016, Texas Instruments Incorporated

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Receiver skew margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter

pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows

for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 150 ps).

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

CLHT

CMOS or LVCMOS low-to-high transition time

See Figure 4

2

3.5

ns

CHLT

CMOS or LVCMOS high-to-low transition time

See Figure 4

1.8

3.5

ns

RSPos0

Receiver input strobe position for bit 0

f = 85 MHz, see Figure 11 and

Figure 12

0.49

0.84

1.19

ns

RSPos1

Receiver input strobe position for bit 1

f = 85 MHz

2.17

2.52

2.87

ns

RSPos2

Receiver input strobe position for bit 2

f = 85 MHz

3.85

4.2

4.55

ns

RSPos3

Receiver input strobe position for bit 3

f = 85 MHz

5.53

5.88

6.23

ns

RSPos4

Receiver input strobe position for bit 4

f = 85 MHz

7.21

7.56

7.91

ns

RSPos5

Receiver input strobe position for bit 5

f = 85 MHz

8.89

9.24

9.59

ns

RSPos6

Receiver input strobe position for bit 6

f = 85 MHz

10.57

10.92

11.27

ns

RSKM

f = 85 MHz, see Figure 13

290

ps

RCOP

RxCLK OUT period

See Figure 5

11.76

T

50

ns

RCOH

RxCLK OUT high time

f = 85 MHz, see Figure 5

4.5

5

7

ns

RCOL

RxCLK OUT low time

f = 85 MHz, see Figure 5

4

5

6.5

ns

RSRC

RxOUT setup to RxCLK OUT

f = 85 MHz, see Figure 5

2

ns

RHRC

RxOUT hold to RxCLK OUT

f = 85 MHz, see Figure 5

3.5

ns

RCCD

RxCLK IN to RxCLK OUT delay

5.5

7

9.5

ns

RPLLS

Receiver phase lock loop set

See Figure 7

10

ms

RPDD

Receiver power down delay

See Figure 10

1

μs

6.7 Timing Diagrams

Figure 1. Test Pattern, Worst Case