DP83849IFVSSLASHNOPB datasheet(29/105 Pages) TI1

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Data

IDLE

Data

(J/K)

(TR)

T2.29.4

T2.29.1

T2.29.5

T2.29.3

T2.29.2

PMD Input

Pair

CRS

RX_DV

RXD[1:0]

RX_ER

Symbol

T2.28.1

T2.28.3

T2.28.2

T2.28.4

TXD[3:0]

TX_EN

PMD Output

Pair

Valid data

DP83849IF

www.ti.com

SNOSAX8D – JUNE 2009 – REVISED APRIL 2013

4.32 AC Specifications — Single Clock MII (SCMII) Transmit Timing

(1)

Parameter

Description

Notes

Min

Typ

Max

Units

T2.28.1

X1 Clock Period

25 MHz Reference Clock

T2.28.2

TXD[3:0], TX_EN Data Setup

To X1 rising

T2.28.3

TXD[3:0], TX_EN Data Hold

From X1 rising

T2.28.4

X1 Clock to PMD Output Pair

100BASE-TX or 100BASE-FX

bits

Latency (100Mb)

(1)

Latency measurement is made from the X1 Rising edge to the first bit of symbol.

4.33 AC Specifications — Single Clock MII (SCMII) Receive Timing

(1) (2) (3)

Parameter

Description

Notes

Min

Typ

Max

Units

T2.29.1

X1 Clock Period

25 MHz Reference Clock

T2.29.2

RXD[3:0], RX_DV and RX_ER output delay

From X1 rising

T2.29.3

CRS ON delay (100Mb)(4)

100BASE-TX mode

bits

100BASE-FX mode

T2.29.4

CRS OFF delay (100Mb)(5)

100BASE-TX mode

bits

100BASE-FX mode

T2.29.5

RXD[1:0] and RX_ER latency (100Mb)

100BASE-TX mode

bits

100BASE-FX mode

(1)

CRS is asserted and deasserted asynchronously relative to the reference clock.

(2)

Output delays assume a 25pF load.

(3)

Receive Latency is measured from the first bit of the symbol pair on the PMD Receive Pair. Typical values are with the Elasticity Buffer

set to the default value (01).

(4)

CRS ON delay is measured from the first bit of the JK symbol on the PMD Receive Pair to assertion of CRS_DV.

(5)

CRS_OFF delay is measured from the first bit of the TR symbol on the PMD Receive Pair to deassertion of CRS_DV.

Electrical Specifications

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