COP8CCR9LVA7SLASHNOPB datasheet(53/111 Pages) TI1

53 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

NOTE

As with the HALT mode, it is necessary to program two NOP's to allow clock

resynchronization upon return from the IDLE mode. The NOP's are placed either at the

beginning of the IDLE Timer interrupt routine or immediately following the “enter IDLE mode”

instruction.

For more information on the IDLE Timer and its associated interrupt, see the description in the Timers

section.

5.12.4 DUAL CLOCK MODE OPERATION

This mode of operation allows for high speed operation of the Core clock and low speed operation of the

Idle Timer. This mode can be entered from either the High Speed mode or the Low Speed mode.

To enter from the High Speed mode, the following sequence must be followed:

1. Software sets the LSON bit to 1.

2. Software waits until the low speed oscillator has stabilized. See Table 5-2.

3. Software sets the DCEN bit to 1.

To enter from the Low Speed mode, the following sequence must be followed:

1. Software sets the HSON bit to 1.

2. Software waits until the high speed oscillator has stabilized. See Table 5-2, Startup Times.

3. Software clears the CCKSEL bit to 0.

5.12.4.1 Dual Clock HALT Mode

The fully static architecture of this device allows the state of the microcontroller to be frozen. This is

accomplished by stopping the high speed clock of the device during the HALT mode. The processor can

be forced to exit the HALT mode and resume normal operation at any time. The low speed clock remains

on during HALT in the Dual Clock mode.

During normal operation, the actual power consumption depends heavily on the clock speed and operating

voltage used in an application and is shown in the Electrical Specifications. In the HALT mode, the device

only draws a small leakage current, plus current for the BOR feature (if enabled), plus the 32 kHz

oscillator current, plus any current necessary for driving the outputs. Since total power consumption is

affected by the amount of current required to drive the outputs, all I/Os should be configured to draw

minimal current prior to entering the HALT mode, if possible.

5.12.4.1.1 Entering The Dual Clock Halt Mode

The device enters the HALT mode under software control when the Port G data register bit 7 is set to 1.

All processor action stops in the middle of the next instruction cycle, and power consumption is reduced to

a very low level. In order to expedite exit from HALT, the low speed oscillator is left running when the

device is Halted in the Dual Clock mode. However, the Idle Timer will not be clocked.

5.12.4.1.2 Exiting The Dual Clock Halt Mode

When the HALT mode is entered by setting bit 7 of the Port G data register, there is a choice of methods

for exiting the HALT mode: a chip Reset using the RESET pin or a Multi-Input Wake-up. The Reset

method and Multi-Input Wake-up method can be used with any clock option.

5.12.4.1.3 HALT Exit Using Reset

A device Reset, which is invoked by a low-level signal on the RESET input pin, takes the device out of the

Dual Clock mode and puts it into the High Speed mode.

Functional Description

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Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

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