AD6635BBSLASHPCB datasheet(14/60 Pages) AD

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AD6635

PIN FUNCTION DESCRIPTION

Name

Type

Function

POWER SUPPLY

VDD

2.5 V Core Supply (also called DVCORE)

VDDIO

3.3 V IO Supply (also called DVRING)

GND

Ground

INPUTS

INA[13:0]

IA Input Data (Mantissa)

EXPA[2:0]

IA Input Data (Exponent)

IENA

Input Enable—Input A

INB[13:0]

IB Input Data (Mantissa)

EXPB[2:0]

IB Input Data (Exponent)

IENB

Input Enable—Input B

INC[13:0]

IC Input Data (Mantissa)

EXPC[2:0]

IC Input Data (Exponent)

IENC

Input Enable—Input C

IND[13:0]

ID Input Data (Mantissa)

EXPD[2:0]

ID Input Data (Exponent)

IEND

Input Enable—Input D

RESET

IActive Low Reset Pin

CLK0

Input Clock 0 (Master Clock for Channels 0–3 and Ports A, B)

CLK1

Input Clock 1 (Master Clock for Channels 4–7 and Ports C, D)

PCLK0

I/O

Link/Parallel Port Clock for Output Ports A and B

PCLK1

I/O

Link/Parallel Port Clock for Output Ports C and D

LACLKIN

Link Port A Data Ready

LBCLKIN

Link Port B Data Ready

LCCLKIN

Link Port C Data Ready

LDCLKIN

Link Port D Data Ready

SYNCA

IAll Sync Pins Go to All Eight Channels

SYNCB

IAll Sync Pins Go to All Eight Channels

SYNCC

IAll Sync Pins Go to All Eight Channels

SYNCD

IAll Sync Pins Go to All Eight Channels

CHIP0_ID[2:0]

IChip ID Selector for Channels 0–3 and Ports A, B

CHIP1_ID[2:0]

IChip ID Selector for Channels 4–7 and Ports C, D

CONTROL

PAACK

Parallel Port A Acknowledge

PAREQ

Parallel Port A Request

PBACK

Parallel Port B Acknowledge

PBREQ

Parallel Port B Request

PCACK

Parallel Port C Acknowledge

PCREQ

Parallel Port C Request

PDACK

Parallel Port D Acknowledge

PDREQ

Parallel Port D Request

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