công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

AD6635BB/PCB bảng dữ liệu(PDF) 8 Page - Analog Devices

tên linh kiện AD6635BB/PCB
Giải thích chi tiết về linh kiện  4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP)
PDF  60 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
Logo AD - Analog Devices

AD6635BB/PCB bảng dữ liệu(HTML) 8 Page - Analog Devices

Back Button AD6635BB/PCB Datasheet HTML 4Page - Analog Devices AD6635BB/PCB Datasheet HTML 5Page - Analog Devices AD6635BB/PCB Datasheet HTML 6Page - Analog Devices AD6635BB/PCB Datasheet HTML 7Page - Analog Devices AD6635BB/PCB Datasheet HTML 8Page - Analog Devices AD6635BB/PCB Datasheet HTML 9Page - Analog Devices AD6635BB/PCB Datasheet HTML 10Page - Analog Devices AD6635BB/PCB Datasheet HTML 11Page - Analog Devices AD6635BB/PCB Datasheet HTML 12Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 60 page
background image
REV. 0
–8–
AD6635
SPECIFICATIONS (continued)
GENERAL TIMING CHARACTERISTICS1, 2
Test
AD6635BB
Parameter (Conditions)
Temp
Level
Min
Typ
Max
Unit
CLKn TIMING REQUIREMENTS
tCLK
CLKn Period
Full
I
12.5
ns
tCLKL
CLKn Width Low
Full
IV
5.6
0.5
tCLK
ns
tCLKH
CLKn Width High
Full
IV
5.6
0.5
tCLK
ns
RESET TIMING REQUIREMENTS
tRESL
RESET Width Low
Full
I
30.0
ns
INPUT WIDEBAND DATA TIMING REQUIREMENTS
tSI
Input to
≠CLKn Setup Time
Full
IV
2.0
ns
tHI
Input to
≠CLKn Hold Time
Full
IV
1.0
ns
LEVEL INDICATOR OUTPUT SWITCHING CHARACTERISTICS
tDLI
≠CLKn to LIx-y Output Delay Time
Full
IV
3.3
10.0
ns
SYNC TIMING REQUIREMENTS
tSS
SYNC(A, B, C, D) to
≠CLKn Setup Time
Full
IV
2.0
ns
tHS
SYNC(A, B, C, D) to
≠CLKn Hold Time
Full
IV
1.0
ns
SERIAL PORT CONTROL TIMING REQUIREMENTS
SWITCHING CHARACTERISTICS
2
tSCLK
SCLKn (n = 0, 4) Period
Full
IV
16
ns
tSCLKL
SCLKn Low Time
Full
IV
3.0
ns
tSCLKH
SCLKn High Time
Full
IV
3.0
ns
INPUT CHARACTERISTICS
tSSI
SDIn to
ØSCLKn Setup Time
Full
IV
1.0
ns
tHSI
SDIn to
ØSCLKn Hold Time
Full
IV
1.0
ns
PARALLEL PORT TIMING REQUIREMENTS
(MASTER MODE) SWITCHING CHARACTERISTICS
3
tDPOCLKL
ØCLKn to ≠PCLKn Delay (Divide by 1)
Full
IV
6.5
10.5
ns
tDPOCLKLL
ØCLKn to ≠PCLKn Delay (Divide by 2, 4, or 8) Full
IV
8.3
14.6
ns
tDPREQ
≠CLKn to ≠PxREQ Delay
1.0
ns
tDPP
≠CLKn to Px[15:0] Delay
0.0
ns
INPUT CHARACTERISTICS
tSPA
PxACK to
ØPCLKn Setup Time
7.0
ns
tHPA
PxACK to
ØPCLKn Hold Time
–3.0
ns
PARALLEL PORT TIMING REQUIREMENTS
(SLAVE MODE) SWITCHING CHARACTERISTICS
3
tPOCLK
PCLKn Period
Full
I
12.5
ns
tPOCLKL
PCLKn Low Period (when PCLK Divisor = 1)
Full
IV
2.0
0.5
tPOCLK
ns
tPOCLKH
PCLKn High Period (when PCLK Divisor = 1)
Full
IV
2.0
0.5
tPOCLK
ns
tDPREQ
≠CLKn to ≠PxREQ Delay
10.0
ns
tDPP
≠CLKn to Px[15:0] Delay
11.0
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com