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AD1985 bảng dữ liệu(PDF) 8 Page - Analog Devices

tên linh kiện AD1985
Giải thích chi tiết về linh kiện  AC ??7 SoundMAX Codec
PDF  48 Pages
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Trang chủ  http://www.analog.com
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AD1985 bảng dữ liệu(HTML) 8 Page - Analog Devices

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AD1985
Rev. A | Page 8 of 48
TIMING PARAMETERS
Guaranteed over operating temperature range.
Table 14.
Parameter
Symbol
Min
Typ
Max
Unit
RESET ACTIVE LOW PULSE WIDTH
tRST_LOW
1.0
µs
RESET INACTIVE TO SDATA_IN OR BIT_CLK ACTIVE DELAY
tRST2CLK
162.8
ns
SYNC ACTIVE HIGH PULSE WIDTH
tSYNC_HIGH
1.3
µs
SYNC LOW PULSE WIDTH
tSYNC_LOW
19.5
µs
SYNC INACTIVE TO BIT_CLK STARTUP DELAY
tSYNC2CLK
162.8
ns
BIT_CLK FREQUENCY
12.288
MHz
BIT_CLK PERIOD
tCLK_PERIOD
81.4
ns
BIT_CLK OUTPUT JITTER1, 2
750
2000
ps
BIT_CLK HIGH PULSE WIDTH
tCLK_HIGH
33
42
48
ns
BIT_CLK LOW PULSE WIDTH
tCLK_LOW
33
38
48
ns
SYNC FREQUENCY
48.0
kHz
SYNC PERIOD
tSYNC_PERIOD
20.8
µs
SETUP TO FALLING EDGE OF BIT_CLK
tSETUP
10
2.5
ns
HOLD FROM FALLING EDGE OF BIT_CLK
tHOLD
5
ns
BIT_CLK RISE TIME
tRISECLK
2
4
6
ns
BIT_CLK FALL TIME
tFALLCLK
2
4
6
ns
SYNC RISE TIME
tRISESYNC
2
4
6
ns
SYNC FALL TIME
tFALLSYNC
2
4
6
ns
SDATA_IN RISE TIME
tRISEDIN
2
4
6
ns
SDATA_IN FALL TIME
tFALLDIN
2
4
6
ns
SDATA_OUT RISE TIME
tRISEDOUT
2
4
6
ns
SDATA_OUT FALL TIME
tFALLDOUT
2
4
6
ns
END OF SLOT 2 TO BIT_CLK, SDATA_IN LOW
tS2_PDOWN
0
1.0
µs
SETUP TO TRAILING EDGE OF RESET (APPLIES TO SYNC, SDATA_OUT)
tSETUP2RST
15.0
ns
RISING EDGE OF RESET TO HIGH-Z DELAY
tOFF
25.0
ns
PROPAGATION DELAY
15
ns
RESET RISE TIME
50
ns
OUTPUT VALID DELAY FROM RISING EDGE OF BIT_CLK TO SDI VALID
tCO
15
ns
RESET INACTIVE TO BIT_CLK STARTUP DELAY
tTRI2ACTV
25
ns
1 Guaranteed, not tested.
2 Output jitter directly dependent on crystal input jitter; maximum specified for noncrystal operation.



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