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DAC7760IPWPR bảng dữ liệu(PDF) 11 Page - Texas Instruments

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tên linh kiện DAC7760IPWPR
Giải thích chi tiết về linh kiện  Single-Channel, 12- and 16-Bit Programmable Current Output and Voltage Output Digital-to-Analog Converters for 4-mA to 20-mA Current Loop Applications
PDF  63 Pages
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nhà sản xuất  TI1 [Texas Instruments]
Trang chủ  http://www.ti.com
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DAC7760IPWPR bảng dữ liệu(HTML) 11 Page - Texas Instruments

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DAC7760, DAC8760
www.ti.com
SBAS528B – JUNE 2013 – REVISED JUNE 2016
Product Folder Links: DAC7760 DAC8760
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Timing Requirements: Write Mode (continued)
At TA = –40°C to 125°C and DVDD = 2.7 V to 5.5 V, unless otherwise noted. See Figure 1 for timing diagram.
PARAMETER(1)
MIN
MAX
UNIT
t9
CLR pulse width
20
ns
t10
CLR activation time
5
μs
(1)
Specified by design, not production tested.
7.8 Timing Requirements: Readback Mode
At TA = –40°C to 125°C and DVDD = 2.7 V to 5.5 V, unless otherwise noted. See Figure 2 for timing diagram.
PARAMETER(1)
MIN
MAX
UNIT
t11
SCLK cycle time
60
ns
t12
SCLK low time
25
ns
t13
SCLK high time
25
ns
t14
LATCH delay time
13
ns
t15
LATCH high time
40
ns
t16
Data setup time
5
ns
t17
Data hold time
7
ns
t18
LATCH low time
40
ns
t19
Serial output delay time (CL, SDO = 15 pF)
35
ns
t20
LATCH rising edge to SDO 3-state (CL, SDO = 15 pF)
35
ns
(1)
Specified by design, not production tested.
7.9 Timing Requirements: Daisy-Chain Mode
At TA = –40°C to 125°C and DVDD = 2.7 V to 5.5 V, unless otherwise noted. See Figure 3 for timing diagram.
PARAMETER(1)
MIN
MAX
UNIT
t21
SCLK cycle time
60
ns
t22
SCLK low time
25
ns
t23
SCLK high time
25
ns
t24
LATCH delay time
13
ns
t25
LATCH high time
40
ns
t26
Data setup time
5
ns
t27
Data hold time
7
ns
t28
LATCH low time
40
ns
t29
Serial output delay time (CL, SDO = 15 pF)
35
ns



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