DP83256 datasheet(125/146 Pages) TI1

tên linh kiện	DP83256

Giải thích chi tiết về linh kiện	PLAYER(TM) Device (FDDI Physical Layer Controller)

PDF	146 Pages

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70 Electrical Characteristics (Continued)

AC Characteristics for the PMD Interface Outputs (ANSI Specifications)

The following output signals are covered PMD Request Data (PMRD) Transmit Clock (TXC) Recovered Data Out

(RXD

OUT) Recovered Clock Out (RXC

OUT)

Note

The Alternate PMD Interface is only available on the 160 pin DP83257 PLAYERa Device and the 100 pin DP83256-AP Device The Transmit Clock is

enabled by the CGMREGTXCE bit The rest of the Alternate PMD Interface is enabled by the APMDREGAPMDEN bit

Comments in square brackets are section references to the ANSI documents where these specifications can be found

Symbol

Parameter

Conditions

Min

Typ

Max

Units

T57

PMRD Total Transmit Jitter

(Note 1)

072

ns p-p

Duty Cycle Distortion (DCD)a

PMD 81

Data Dependent Jitter (DDJ)a

Random Jitter (RJ)

T58

Total Recovered Clock (RXC

OUT) Jitter

(Note 1)

ns p-p

Static Alignment Error Accuracy (SAE)a

PMD E2

Clock Data Dependent Jitter (C

DDJ)a

Random Jitter (C

RJ)

Note 1

This parameter is not tested but is assured through characterization data and periodic testing of sample units

124

DP83256 bảng dữ liệu(PDF) 125 Page - Texas Instruments