DP83256 datasheet(124/146 Pages) TI1

tên linh kiện	DP83256

Giải thích chi tiết về linh kiện	PLAYER(TM) Device (FDDI Physical Layer Controller)

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70 Electrical Characteristics (Continued)

AC Characteristics for the PMD Interface Inputs (ANSI Specifications)

The following input signals are covered PMD Indicate Data (PMID) Receive Data In (RXD

IN) Receive Clock In (RXC

IN)

Note

The Alternate PMD Interface is only available on the 160 pin DP83257 PLAYERa Device and the 100 pin DP83256-AP Device The Transmit Clock is

enabled by the CGMREGTXCE bit The rest of the Alternate PMD Interface is enabled by the APMDREGAPMDEN bit

All comments in square brackets are section references to the ANSI documents where these specifications can be found

Symbol

Parameter

Conditions

Min

Typ

Max

Units

T53

CRM Window Recognition Region

PMD E2

(PMID Inputs)

T54

PMID Receive Clock Tolerance

PHY 524

100

ppm

(Lock Acquisition Range)

T55

Receive Clock Acquisition Time

From 1st Data

100

and SD Active

PHY 526

T56

Receive Clock Acquisition Time

From Line State

Change

PHY 526

TLF11708 – 54

TLF11708 – 55

FIGURE 7-13 Alternate PMD Input Timing DiagramsANSI Specifications

123

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