DAC5686IPZP datasheet(48/53 Pages) TI1

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DAC5686 EVALUATION BOARD

APPENDIX A. PLL LOOP FILTER COMPONENTS

DESIGNING THE PLL LOOP FILTER

External

Internal

S0006-01

DAC5686

SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com

There is a combination EVM board for the DAC5686 digital-to-analog converter for evaluation. This board allows

the user the flexibility to operate the DAC5686 in various configurations. Possible output configurations include

transformer-coupled, resistor-terminated, inverting/non-inverting and differential amplifier outputs. The digital

inputs are designed to be driven directly from various pattern generators with the onboard option to add a

resistor network for proper load termination.

The DAC5686 contains an external loop filter to set the bandwidth and phase margin of the PLL. For the external

second-order filter shown in Figure 53, the components R1, C1, and C2 are set by the user to optimize the PLL

for the application. The resistance R3 = 200

Ω and the capacitance C3 = 8 pF are internal to the DAC5686. Note

that the positions of R1 and C1 can be reversed, relative to each other.

Figure 53. DAC5686 Loop Filter

The typical VCO gain (Gvco) (the slope of VCO frequency vs voltage) as a function of VCO frequency for the

DAC5686 is shown in Figure 17. The VCO frequency range can be extended to higher frequencies by setting the

pll_rng[1:0] registers to increase the VCO Vtol current (see Table 11). However, only the range for PLL_rng = 00

(nominal) is specified.

For the lowest possible phase noise, the VCO frequency should be chosen so Gvco is minimized, where

fvco = fdata × Interpolation × PLL Divider

For example, if fdata = 125 MSPS and 2× interpolation is used, the PLL divider should be set to 2 to lock the VCO

at 500 MHz for a typical Gvco of 200 MHz/V.

The external loop filter components C1, C2, and R1 are determined by choosing Gvco, N = fvco/fdata, the loop

phase margin

d, and the loop bandwidth ωd. Except for applications where abrupt clock frequency changes

require a fast PLL lock time, it is suggested that

d be set to at least 80 degrees for stable locking and

suppression of the phase-noise side lobes. Phase margins of 60 degrees or less occasionally have been

sensitive to board layout and decoupling details.

The optimum loop bandwidth

d depends on both the VCO phase noise, which is largely a function of Gvco, and

the application. For the example above with Gvco = 200 MHz/V, an

d = 1 MHz would be typical, but lower or

higher loop bandwidths may provide better phase noise characteristics. For a higher Gvco, for example

Gvco = 400 MHz/V, an

d ~ 7 MHz would be typical. However, it is suggested that customers experiment with

varying the loop bandwidth at least from × to 2× to verify the optimum setting.

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