CC1021-RTR1 datasheet(63/91 Pages) TI1

63 / 91 page

Not Recommended for New Designs NRND

CC1021

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SWRS045D – JANUARY 2006 – REVISED JANUARY 2015

Table 5-20. RESET Register (02h)(1)(2)

DEFAULT

NAME

ACTIVE

DESCRIPTION

VALUE

RESET[7]

ADC_RESET_N

Reset ADC control logic

RESET[6]

AGC_RESET_N

Reset AGC (VGA control) logic

RESET[5]

GAUSS_RESET_N

Reset Gaussian data filter

RESET[4]

AFC_RESET_N

Reset AFC / FSK decision level logic

RESET[3]

BITSYNC_RESET_N

Reset modulator, bit synchronization logic and PN9 PRBS generator

RESET[2]

SYNTH_RESET_N

Reset digital part of frequency synthesizer

RESET[1]

SEQ_RESET_N

Reset power-up sequencing logic

RESET[0]

CAL_LOCK_RESET_N

Reset calibration logic and lock detector

(1)

For reset of CC1020 write RESET_N=0 in the MAIN register. The reset register should not be used during normal operation.

(2)

Bits in the RESET register are self-clearing (will be set to 1 when the reset operation starts). Relevant digital clocks must be running for

the resetting to complete. After writing to the RESET register, the user should verify that all reset operations have been completed, by

reading the RESET_DONE status register (41h) until all bits equal 1.

Table 5-21. SEQUENCING Register (03h)

DEFAULT

NAME

ACTIVE

DESCRIPTION

VALUE

SEQUENCING[7]

SEQ_PSEL

Use PSEL pin to start sequencing

0: PSEL pin does not start sequencing. Negative transitions on

DIO starts power-up sequencing if SEP_DI_DO=1.

1: Negative transitions on the PSEL pin will start power-up

sequencing

SEQUENCING[6:4]

RX_WAIT[2:0]

—

Waiting time from PLL enters lock until RX power up

0: Wait for approx. 32 ADC_CLK periods (26

μs)

1: Wait for approx. 44 ADC_CLK periods (36

μs)

2: Wait for approx. 64 ADC_CLK periods (52

μs)

3: Wait for approx. 88 ADC_CLK periods (72

μs)

4: Wait for approx. 128 ADC_CLK periods (104

μs)

5: Wait for approx. 176 ADC_CLK periods (143

μs)

6: Wait for approx. 256 ADC_CLK periods (208

μs)

7: No additional waiting time before RX power up

SEQUENCING[3:0]

CS_WAIT[3:0]

—

Waiting time for carrier sense from RX power up

0: Wait 20 FILTER_CLK periods before power down

1: Wait 22 FILTER_CLK periods before power down

2: Wait 24 FILTER_CLK periods before power down

3: Wait 26 FILTER_CLK periods before power down

4: Wait 28 FILTER_CLK periods before power down

5: Wait 30 FILTER_CLK periods before power down

6: Wait 32 FILTER_CLK periods before power down

7: Wait 36 FILTER_CLK periods before power down

8: Wait 40 FILTER_CLK periods before power down

9: Wait 44 FILTER_CLK periods before power down

10: Wait 48 FILTER_CLK periods before power down

11: Wait 52 FILTER_CLK periods before power down

12: Wait 56 FILTER_CLK periods before power down

13: Wait 60 FILTER_CLK periods before power down

14: Wait 64 FILTER_CLK periods before power down

15: Wait 72 FILTER_CLK periods before power down

Table 5-22. FREQ_2A Register (04h)

DEFAULT

NAME

ACTIVE

DESCRIPTION

VALUE

FREQ_2A[7:0]

FREQ_A[22:15]

131

—

8 MSB of frequency control word A

Detailed Description

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