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PC33889 bảng dữ liệu(PDF) 5 Page - Motorola, Inc

tên linh kiện PC33889
Giải thích chi tiết về linh kiện  System Basis Chip Lite with Low Speed Fault Tolerant CAN Interface
PDF  30 Pages
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

PC33889 bảng dữ liệu(HTML) 5 Page - Motorola, Inc

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PC33889
5
PC33889
Low Level Output Voltage (I0=1.5mA)
Vol
0
0.9
V
5.5v<Vsup<27V
High Level Output Voltage (I0=-250uA)
Voh
Vdd1-0.9
Vdd1
INT Pin
Low Level Output Voltage (I0=1.5mA)
Vol
0
0.9
V
High Level Output Voltage (I0=-250uA)
Voh
Vdd1-0.9
Vdd1
HS1: 150mA High side output pin
Rdson at Tj=25°C, and Iout -150mA
Rdson25
2.5
Ohms
Vsup>9V
Rdson at Tj=125°C, and Iout -150mA
Rdson125
5
Ohms
Vsup>9V
Rdson at Tj=125°C, and Iout -120mA
Ron125-2
4
5.5
Ohms
5.5V<Vsup<9V
Output current limitation
Ilim
200
500
mA
Over temperature Shutdown
Ovt
155
190
°C
Leakage current
Ileak
10
uA
Output Clamp Voltage at Iout= -1mA
Vcl
-1.5
-0.3
V
no inductive load drive capa-
bility
Cyclic sense period (refer to SPI)
T1
ms
in sleep and stop modes
Cyclic sense On time (refer to SPI)
T2
100
us
in sleep and stop modes
Timing accuracy (cyclic sense period and
on time)
Tacc
-30
+30
%
in sleep and stop mode
L0 and L1 inputs
L0 Negative Switching Threshold
Vth0n
1.7
2
2
tbd
tbd
3
3
3.1
V
5.5V<Vsup<6V
6V<Vsup<18V
18V<Vsup<27V
L0 Positive Switching Threshold
Vth0p
2.2
2.5
2.5
tbd
tbd
4
4
4.1
V
5.5V<Vsup<6V
6V<Vsup<18V
18V<Vsup<27V
L1 Negative Switching Threshold
Vth1n
2
2.5
2.7
2.5
3
3.2
3
3.6
3.7
V
5.5V<Vsup<6V
6V<Vsup<18V
18V<Vsup<27V
L1 Positive Switching Threshold
Vth1p
2.7
3
3.5
3.3
4
4.2
3.8
4.6
4.7
V
5.5V<Vsup<6V
6V<Vsup<18V
18V<Vsup<27V
Hysteresis
Vhyst
0.6
tbd
1.3
V
5.5V<Vsup<18V
18V<Vsup<27V
Input current
Iin
-10
10
uA
-0.2V < Vin < 40V
Wake up Filter Time (enable/disable
option on L0 input)
820
38
us
(If filter enable)
DIGITAL INTERFACE TIMING
SPI operation frequency
Freq
4
MHz
SCLK Clock Period
tpCLK
250
ns
SCLK Clock High Time
twSCLKH
125
ns
SCLK Clock Low Time
twSCLKL
125
ns
Falling Edge of CS to Rising
Edge of SCLK
tlead
100
50
ns
Falling Edge of SCLK to Rising Edge of
CS
tlag
100
50
ns
MOSI to Falling Edge of SCLK
tSISU
40
25
ns
Falling Edge of SCLK to MOSI
tSIH
40
25
ns
MISO Rise Time (CL = 220pF)
trSO
25
50
ns
MISO Fall Time (CL = 220pF)
tfSO
25
50
ns
(Vsup From 5.5V to 18V and Tj from -40°C to 125°C) unless otherwise noted. For all pins except can related pins
Description
Symbol
Characteristics
Unit
Conditions
Min
Typ
Max
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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