TUSB3410 datasheet(62/92 Pages) TI

62 / 92 page

9–2

9.1.3

VECINT: Vector Interrupt Register (Addr:FF92)

This register contains a vector value, which identifies the internal interrupt source that trapped to location 0003H.

Writing (any value) to this register removes the vector and updates the next vector value (if another interrupt is

pending). Note: the vector value is offset; therefore, its value is in increments of two (bit 0 is set to 0). When no interrupt

is pending, the vector is set to 00h (see Table 9–2). As shown, the interrupt vector is divided to two fields: I[2:0] and

G[3:0]. The I field defines the interrupt source within a group (on a first-come-first-served basis). In the G field, which

defines the group number, group G0 is the lowest, and G15 is the highest priority.

765

R/O

BIT

NAME

RESET

FUNCTION

3–1

I[2:0]

This field defines the interrupt source in a given group. See Table 9–2. Bit 0 = 0 always; therefore, vector values

are offset by two.

7–4

G[3:0]

This field defines the interrupt group. I[2:0] and G[3:0] combine to produce the actual interrupt vector.

Table 9–2. Vector Interrupt Values

G[3:0]

(Hex)

I[2:0]

(Hex)

VECTOR

(Hex)

INTERRUPT SOURCE

No interrupt

Not used

Output endpoint-1

Output endpoint-2

Output endpoint-3

Not used

Input endpoint-1

Input endpoint-2

Input endpoint-3

STPOW packet received

SETUP packet received

RESERVED

RESR interrupt

SUSR interrupt

RSTR interrupt

Reserved

I2C TXE interrupt

I2C RXF interrupt

Input endpoint-0

Output endpoint-0

4–7

→ 4E

Not used

4–7

→ 5E

UART status interrupt

UART modem interrupt

Not used

4–7

5–7

→ 6E

→ 7E

UART RXF interrupt

UART TXE interrupt

Not used

5–7

88–8E

DMA1 interrupt

DMA3 interrupt

Not used

9–15

→ FE

Not used

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