TUSB3410 datasheet(47/92 Pages) TI

47 / 92 page

7–1

7 UART

7.1

UART Registers

Table 7–1 summarizes the UART registers. These registers are used for data I/O, control, and status information.

UART setup is done by the MCU. Data transfer is typically performed by the DMAC. However, the MCU can perform

data transfer without DMA; this is useful when debugging the firmware.

Table 7–1. UART Registers Summary

ACCESS

FUNCTION

COMMENTS

RDR

R/O

UART receiver data register

Can be accessed by MCU or DMA

TDR

W/O

UART transmitter data register

Can be accessed by MCU or DMA

LCR

R/W

UART line control register

FCRL

R/W

UART flow control register

MCR

R/W

UART modem control register

LSR

R/O

UART line status register

Can generate an interrupt

MSR

R/O

UART modem status register

Can generate an interrupt

DLL

R/W

UART divisor register (low byte)

DLH

R/W

UART divisor register (high byte)

XON

R/W

UART Xon register

XOFF

R/W

UART Xoff register

MASK

R/W

UART interrupt mask register

Can control three interrupt sources

7.1.1

RDR: Receiver Data Register (Addr:FFA0)

The receiver data register consists of a 32-byte FIFO. Data received from the SIN pin are converted from

serial-to-parallel format and stored in this FIFO. Data transfer from this register to the RAM buffer is the responsibility

of the DMA controller.

765

R/O

BIT

NAME

RESET

FUNCTION

7–0

D[7:0]

Receiver byte

7.1.2

TDR: Transmitter Data Register (Addr:FFA1)

The transmitter data register is double buffered. Data written to this register is loaded into the shift register, and shifted

out on SOUT. Data transfer from the RAM buffer to this register is the responsibility of the DMA controller.

765

W/O

BIT

NAME

RESET

FUNCTION

7–0

D[7:0]

Transmit byte

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