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PCM1721 bảng dữ liệu(PDF) 12 Page - Burr-Brown (TI) |
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PCM1721 bảng dữ liệu(HTML) 12 Page - Burr-Brown (TI) |
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12 / 16 page ![]() ® 12 PCM1721 SF1 SF0 Sampling Frequency 0 0 44.1kHz group 22.05/44.1/88.2kHz 0 1 48kHz group 24/48/96kHz 1 0 32kHz group 16/32/64kHz 1 1 Reserved Not Defined Bits 6 (SF0) and 7 (SF1) are used to select the sampling frequency: Bit 8 is used to control the infinite zero detection function (IZD). When IZD is “LOW”, the zero detect circuit is off. Under this condition, no automatic muting will occur if the input is continuously zero. When IZD is “HIGH”, the zero detect feature is enabled. If the input data is continuously zero for 65, 536 cycles of BCKIN, the output will be immediately forced to a bipolar zero state (V CC/2). The zero detection feature is used to avoid noise which may occur when the input is DC. When the output is forced to bipolar zero, there may be an audible click. PCM1721 allows the zero detect feature to be disabled so the user can implement an external muting circuit. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 ML (pin 6) MC (pin 7) MD (pin 8) FIGURE 7. Serial Interface Timing. FIGURE 8. Program Register Input Timing. 1.4V 1.4V 1.4V ML MC MD MC Pulse Cycle Time MC Pulse Width LOW MC Pulse Width HIGH MD Set-up Time MC Hold Time ML Low Level Time ML Set-up Time ML Hold Time : t MCY : t MCL : t MCH : t MDS : t MDH : t MLL : t MLS : t MLH : 100ns (min) : 50ns (min) : 50ns (min) : 30ns (min) : 30ns (min) : 30ns + 1SYSCLK (min) : 30ns (min) : 30ns (min) t MCY t MDS t MDH t MCH t MCL t MLS t MLH t MLL |
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