1-323

Optically Coupled 20 mA

Current Loop Receiver

Technical Data

HCPL-4200

Features

• Data Output Compatible

with LSTTL, TTL and CMOS

• 20 K Baud Data Rate at 1400

Metres Line Length

• Guaranteed Performance

over Temperature (0°C to

70°C)

• Guaranteed On and Off

Thresholds

• LED is Protected from

Excess Current

• Input Threshold Hysteresis

• Three-State Output Compat-

ible with Data Buses

• Internal Shield for High

Common Mode Rejection

• Safety Approval

UL Recognized -2500 V rms,

for 1 Minute

CSA Approved

• Optically Coupled 20 mA

Current Loop Transmitter,

HCPL-4100, Also Available

Applications

• Isolated 20 mA Current

• Loop Receiver in:

Computer Peripherals

Industrial Control Equipment

Data Communications

Equipment

Description

The HCPL-4200 optocoupler is

designed to operate as a receiver

in equipment using the 20 mA

Current Loop. 20 mA current

loop systems conventionally sig-

nal a logic high state by transmit-

ting 20 mA of loop current

(MARK), and signal a logic low

state by allowing no more than a

few milliamperes of loop current

(SPACE). Optical coupling of the

signal from the 20 mA current

loop to the logic output breaks

ground loops and provides for a

very high common mode

rejection. The HCPL-4200 aids in

the design process by providing

guaranteed thresholds for logic

high state and logic low state for

the current loop, providing an

LSTTL, TTL, or CMOS compatible

logic interface, and providing

guaranteed common mode

rejection. The buffer circuit on

the current loop side of the

HCPL-4200 provides typically 0.8

mA of hysteresis which increases

the immunity to common mode

and differential mode noise. The

buffer also provides a controlled

amount of LED drive current

which takes into account any

LED light output degradation.

The internal shield allows a

guaranteed 1000 V/µs common

mode transient immunity.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to

prevent damage and/or degradation which may be induced by ESD.

Functional Diagram

A 0.1 µF bypass capacitor connected between pins 8 and 5 is recommended.

5965-3580E