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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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HCPL4200 bảng dữ liệu(PDF) 7 Page - Agilent(Hewlett-Packard) |
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HCPL4200 bảng dữ liệu(HTML) 7 Page - Agilent(Hewlett-Packard) |
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7 / 12 page  1-329 Notes: 1. ≤ 1 µs pulse width, 300 pps. 2. Derate linearly above 70°C free air temperature at a rate of 1.6 mW/ °C. Proper application of the derating factors will prevent IC junction temperatures from exceeding 125°C for ambient temperatures up to 85°C. 3. Derate linearly above 70°C free air temperature at a rate of 3.8 mW/ °C. 4. Derate linearly above 70°C free air temperature at a rate of 4.6 mW/ °C. 5. Duration of output short circuit time shall not exceed 10 ms. 6. The device is considered a two terminal device, pins 1, 2, 3, and 4 are connected together and pins 5, 6, 7, and 8 are connected together. 7. The tPLH propagation delay is measured from the 10 mA level on the leading edge of the input pulse to the 1.3 V level on the leading edge of the output pulse. 8. The tPHL propagation delay is measured from the 10 mA level on the trailing edge of the input pulse to the 1.3 V level on the trailing edge of the output pulse. 9. The rise time, tr, is measured from the 10% to the 90% level on the rising edge of the output logic pulse. 10. The fall time, tf, is measured from the 90% to the 10% level on the falling edge of the output logic pulse. 11. Common mode transient immunity in the logic high level is the maximum (negative) dVCM/dt on the trailing edge of the common mode pulse, VCM, which can be sustained with the output voltage in the logic high state (i.e., VO ≥ 2 V). 12. Common mode transient immunity in the logic low level is the maximum (positive) dVCM/dt on the leading edge of the common mode pulse, VCM, which can be sustained with the output voltage in the logic low state (i.e., VO ≤ 0.8 V). 13. Use of a 0.1 µF bypass capacitor connected between pins 5 and 8 is recommended. 14. In accordance with UL 1577, each optocoupler momentary withstand is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (leakage detection current limit, Ii-o ≤ 5 µA). Figure 5. Typical Input Voltage vs. Temperature. Figure 6. Typical Logic Low Output Voltage vs. Temperature. Figure 7. Typical Logic High Output Current vs. Temperature. Figure 2. Typical Output Voltage vs. Loop Current. Figure 3. Typical Current Switching Threshold vs. Temperature. Figure 4. Typical Input Loop Voltage vs. Input Current. |
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