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COP884CL-XXX/WM bảng dữ liệu(PDF) 9 Page - National Semiconductor (TI) |
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COP884CL-XXX/WM bảng dữ liệu(HTML) 9 Page - National Semiconductor (TI) |
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9 / 40 page ![]() DC Electrical Characteristics b55 C s TA s a25 C unless otherwise specified (Continued) Parameter Conditions Min Typ Max Units Allowable SinkSource Current per Pin D Outputs (Sink) 12 mA All others 25 mA Maximum Input Current 150 mA without Latchup (Note 4) RAM Retention Voltage Vr 500 ns Rise 20 V and Fall Time (Min) Input Capacitance 7pF Load Capacitance on D2 1000 pF Note 1 Rate of voltage change must be less then 05 Vms Note 2 Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open Note 3 The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations Test conditions All inputs tied to VCC L and G ports in the TRI- STATE mode and tied to ground all outputs low and tied to ground The Clock Monitor and the comparators are disabled AC Specifications for COP688CL AC Electrical Characteristics b55 C s TA s a125 C unless otherwise specified Parameter Conditions Min Typ Max Units Instruction Cycle Time (tc) Crystal Resonator or VCC t 45V 1DC m s External Oscillator RC Oscillator (div-by 10) VCC t 45V 3 DC m s Inputs tSETUP VCC t 45V 200 ns tHOLD VCC t 45V 60 ns Output Propagation Delay (Note 5) RL e 22k CL e 100 pF tPD1 tPD0 SO SK VCC t 45V 07 m s All Others VCC t 45V 1 m s MICROWIRE Setup Time (tUWS)20 ns MICROWIRE Hold Time(tUWH)56 ns MICROWIRE Output Propagation Delay (tUPD) 220 ns Input Pulse Width Interrupt Input High Time 1 tc Interrupt Input Low Time 1 tc Timer Input High Time 1 tc Timer Input Low Time 1 tc Reset Pulse Width 1 m s Note 4 Pins G6 and RESET are designed with a high voltage input network for factory testing These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC) The effective resistance to VCC is 750X (typical) These two pins will not latch up The voltage at the pins must be limited to less than 14V Note 5 The output propagation delay is referenced to the end of the instruction cycle where the output change occurs http www nationalcom 9 |
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