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COP884CL-XXX/WM bảng dữ liệu(PDF) 7 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện COP884CL-XXX/WM
Giải thích chi tiết về linh kiện  General Description
PDF  40 Pages
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nhà sản xuất  NSC [National Semiconductor (TI)]
Trang chủ  http://www.national.com
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COP884CL-XXX/WM bảng dữ liệu(HTML) 7 Page - National Semiconductor (TI)

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DC Electrical Characteristics b40 C s TA s a85 C unless otherwise specified (Continued)
Parameter
Conditions
Min
Typ
Max
Units
Allowable SinkSource
Current per Pin
D Outputs (Sink)
15
mA
All others
3mA
Maximum Input Current
TA e 25 C
g
100
mA
without Latchup (Note 4)
RAM Retention Voltage Vr
500 ns Rise
2V
and Fall Time (Min)
Input Capacitance
7pF
Load Capacitance on D2
1000
pF
AC Electrical Characteristics b40 C s TA s a85 C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (tc)
Crystal or Resonator
4V s VCC s 6V
1
DC
m
s
25V s VCC k 4V
25
DC
m
s
RC Oscillator
4V s VCC s 6V
3
DC
m
s
25V s VCC k 4V
75
DC
m
s
Inputs
tSETUP
4V s VCC s 6V
200
ns
25V s VCC k 4V
500
ns
tHOLD
4V s VCC s 6V
60
ns
25V s VCC k 4V
150
ns
Output Propagation Delay (Note 5)
RL e 22k CL e 100 pF
tPD1 tPD0
SO SK
4V s VCC s 6V
07
m
s
25V s VCC k 4V
175
m
s
All Others
4V s VCC s 6V
1
m
s
25V s VCC k 4V
25
m
s
MICROWIRE Setup Time (tUWS)20
ns
MICROWIRE Hold Time (tUWH)56
ns
MICROWIRE Output Propagation Delay (tUPD)
220
ns
Input Pulse Width
Interrupt Input High Time
1
tc
Interrupt Input Low Time
1
tc
Timer Input High Time
1
tc
Timer Input Low Time
1
tc
Reset Pulse Width
1
m
s
Note 4
Pins G6 and RESET are designed with a high voltage input network for factory testing These pins allow input voltages greater than VCC and the pins will
have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC) The effective
resistance to VCC is 750X (typical) These two pins will not latch up The voltage at the pins must be limited to less than 14V
Note 5
The output propagation delay is referenced to the end of the instruction cycle where the output change occurs
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