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DS1921 bảng dữ liệu(PDF) 41 Page - Dallas Semiconductor

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Giải thích chi tiết về linh kiện  High-Resolution Thermochron iButton
PDF  44 Pages
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DS1921 bảng dữ liệu(HTML) 41 Page - Dallas Semiconductor

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DS1921H/Z
41 of 44
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
IO pin, 1-Wire Reset, Presence Detect Cycle
Standard Speed,
VPUP > 4.5V
480
640
Reset Low Time
tRSTL
Standard Speed
540
640
µs
1, 15
Overdrive Speed
48
80
Presence Detect High
tPDH
Standard Speed
15
60
µs
15
Time
Overdrive Speed
1.1
6
Presence Detect Low
tPDL
Standard Speed
60
270
µs
15
Time
Overdrive Speed
7.5
24
Presence Detect
tMSP
Standard Speed
60
75
µs
1, 16
Sample Time
Overdrive Speed
6
8.6
IO pin, 1-Wire Write
Write-0 Low Time
tW0L
Standard Speed
60
120
µs
1, 15
Overdrive Speed
6
15
Write-1 Low Time
tW1L
Standard Speed
5
15 -
ε
µs
1, 11
Overdrive Speed
1
2 -
ε
IO pin, 1-Wire Read
Read Low Time
tRL
Standard Speed
5
15 -
δ
µs
1, 12
Overdrive Speed
1
2 -
δ
Read Sample Time
tMSR
Standard Speed
tRL +
δ
15
µs
1, 12
Overdrive Speed
tRL +
δ
2
Real-Time Clock
Frequency Deviation
∆
F
-5°C to +46°C
-48
+46
PPM
Temperature Converter
Tempcore Operating
TTC
DS1921H
15
46
°C
Range
DS1921Z
-5
+26
Conversion Time
tCONV
75
360
ms
Thermal Response
Time Constant
τ
RESP
130
s
13
Conversion Error
∆ϑ
-1
+1
°C
17, 18
Number of
Conversions
NCONV
(see graphs)
—
14, 16
NOTES
1) System Requirement.
2) Maximum allowable pull-up resistance is a function of the number of 1-Wire devices in the
system and 1-Wire recovery times. The specified value here applies to systems with only one
device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active
pull-up such as that found in the DS2480B may be required.
3) Capacitance on IO could be 800pF when power is first applied. If a 2.2k
Ω resistor is used to pull
up the data line, 2.5µs after VPUP has been applied the parasite capacitor will not affect normal
communication.
4)
Input load is to ground.
5) All voltages are referenced to ground.
6) VTL, VTH are a function of the internal supply voltage.
7) Voltage below which, during a falling edge on IO, a logic 0 is detected.
8) The voltage on IO needs to be less or equal to VILMAX whenever the master drives the line low.



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