CLC011 datasheet(5/8 Pages) NSC

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Overview

The CLC011, Serial Digital Video Decoder, decodes and de-

scrambles SMPTE 259M standard Serial Digital Video

datastreams into 10-bit parallel words and a corresponding

word-rate clock. The following information describes:

•

the CLC011 operation,

•

recommended interface circuitry, and

•

PCB layout suggestions.

Applications assistance for the CLC011 may be obtained by

calling the Interface Applications Hotline, (408) 721-8500.

Input Interfacing — Signal Inputs

The serial data and clock inputs of the CLC011 are both dif-

ferential. Their input voltage ranges from 2.5V above the

negative supply (V

EE +2.5V) to the positive supply voltage

CC). Supply voltages for the CLC011 may be either +5V or

–5.2V for ECL compatibility and interfacing. When operated

from the negative supply, inputs accept standard ECL signal

levels. The minimum differential input swing is 200 mV. The

CLC011 interfaces with the CLC016 Data Retiming PLL as

shown in

Figure 2. A simplified schematic of the CLC011’s

signal inputs appears in

Figure 3.

Input Interfacing — Control Inputs

Three TTL-compatible inputs control operation of the

CLC011: NRZI, DESC and FE. A typical interface circuit for

the control inputs is shown in

Figure 4.

NRZI: NRZI, when a logic high, enables NRZI to NRZ con-

version. For standard SMPTE 259M operation, NRZI is high.

DESC

(Descramble): The

bits

SMPTE

259M

datastream are scrambled upon encoding according to a

polynomial equation. DESC, when a logic high, enables de-

scrambling of the encoded signal. For standard SMPTE

259M operation, DESC is high.

FE (Framing Enable): SMPTE 259M datastreams include a

four-word-long reserved sequence known as the Timing Ref-

erence Signal (TRS). Using this sequence, the CLC011 de-

termines the position of word boundaries, also known as

framing, of the incoming data.

The FE input, when a logic high and following recognition of

a TRS, causes the CLC011 to automatically adjust its fram-

ing. The word boundary is aligned at the appropriate bit po-

sition and the parallel output clock is aligned with the appro-

priate cycle of the serial clock. When FE is held low and a

TRS, out of phase with the current PCLK, is received, output

NSP will go high. However, the phase of PCLK will not be ad-

justed. NSP will remain high until a TRS, in-phase with the

current PCLK, is received.

DS100086-4

FIGURE 2. Interface with CLC016

DS100086-5

FIGURE 3. Simplified Input Buffer Schematic

DS100086-6

FIGURE 4. Typical Control Logic Connection

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