PI6CDBL402B datasheet(12/13 Pages) PERICOM

12 / 13 page

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06/30/15

PI6CDBL402B

4 -Output Low Power PCIE GEN 1-2-3 Buffer

Electrical Characteristics–Phase Jitter Parameters (T

A = -40~85

C; VDD = 3.3V+/-10%; VDDO =

3.3V+/-10%, VDDO = 2.5V+/-10%, VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions)

Symbol

Parameters

Condition

Min. Type

Industry

Limit

Units

jphPCIeG1

Phase Jitter,

PLL Mode

PCIe Gen 11,2,3

(p-p)

jphPCIeG2

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz1,2

0.9

(rms)

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)1,2

2.2

3.1

(rms)

jphPCIeG3

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)1,2,3,4

0.5

(rms)

jphSGMII

125MHz, 1.5MHz to 20MHz, -20dB/decade rollover <

1.5MHz, -40db/decade rolloff > 10MHz1,6

1.9

(rms)

jphPCIeG1

Additive

Phase Jitter,

Bypass Mode

PCIe Gen 11,2,3

0.6

N/A

(p-p)

jphPCIeG2

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz1,2,5

0.1

N/A

(rms)

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)1,2,5

0.05

N/A

(rms)

jphPCIeG3

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)1,2,4,5

0.05

N/A

(rms)

jphSGMII

125MHz, 1.5MHz to 10MHz, -20dB/decade rollover <

1.5MHz, -40db/decade rolloff > 10MHz1,6

0.15

N/A

(rms)

Note:

1. Applies to all outputs, with device driven by 9FG432AKLF or equivalent.

2. See http://www.pcisig.com for complete specs

3. Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

4. Subject to final ratification by PCI SIG.

5. For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]

6. Applies to all differential outputs

15-0083

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