BQ76PL536APAPR datasheet(13/74 Pages) TI1

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t CS,LEAD

t CS,LAG

t(SCLK )

SCLK

t(HIGH)

t(LOW)

SDI

tSU,SDI

tHD,SDI

SDO

tACC

tVALID, SDO

tDIS

t CS _ DLY

bq76PL536A

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SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

6.7 Vertical Communications Bus

Typical values stated where TA = 25ºC and VBAT = 20 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

tHV_SCLK

Propagation delay, SCLK_H to SCLK_N

HOST = 0

tVB_SCLK

Propagation delay, SCLK_S to SCLK_N

HOST = 1

tHV_CS

Propagation delay, CS_H to CS_N

HOST = 0

tVB_CS

Propagation delay, CS_S to CS_N

HOST = 1

tHV_SDI

Propagation delay, SDI_H to SDI_N

HOST = 0

tVB_SDI

Propagation delay, SDI_S to SDI_N

HOST = 1

tHV_CONV

Propagation delay, CONV_H to CONV_N

HOST = 0

100

tVB_CONV

Propagation delay, CONV_S to CONV_N

HOST = 1

tHV_SDO

Propagation delay, SDO_N to SDO_H

HOST = 0

tVB_SDO

Propagation delay, SDO_N to SDO_S

HOST = 1

tHV_DRDY

Propagation delay, DRDY_N to DRDY_H

HOST = 0

tVB_DRDY

Propagation delay, DRDY_N to DRDY_S

HOST = 1

tHV_FAULT

Propagation delay, FAULT_N to FAULT_H

HOST = 0

tVB_FAULT

Propagation delay, FAULT_N to FAULT_S

HOST = 1

tHV_ALERT

Propagation delay, ALERT_N to ALERT_H

HOST = 0

tVB_ALERT

Propagation delay, ALERT_N to ALERT_S

HOST = 1

(1)

Typical values are quoted in place of MIN/MAX for design guidance only. Actual propagation delay depends heavily on wiring and

capacitance in the signal path. These parameters are not tested in production due to these dependencies on system design

considerations.

Figure 1. SPI Host Interface Timing

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