AD6679 datasheet(5/81 Pages) AD

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Data Sheet

AD6679

Rev. B | Page 5 of 81

SPECIFICATIONS

DC SPECIFICATIONS

AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling

rate, 1.0 V internal reference (VREF), AIN = −1.0 dBFS, clock divider = 2, default SPI settings, unless otherwise noted.

Table 1.

Parameter

Temperature

Min

Typ

Max

Unit

RESOLUTION

Bits

ACCURACY

No Missing Codes

Full

Guaranteed

Offset Error

Full

−0.3

+0.3

% FSR

Offset Matching

Full

0.3

% FSR

Gain Error

Full

−6.5

+6.5

% FSR

Gain Matching

Full

5.0

% FSR

Differential Nonlinearity (DNL)

Full

−0.6

±0.5

+0.7

LSB

Integral Nonlinearity (INL)

Full

−4.5

±2.5

+5.0

LSB

TEMPERATURE DRIFT

Offset Error

Full

±3

ppm/°C

Gain Error

Full

−39

ppm/°C

INTERNAL VOLTAGE REFERENCE

Voltage

Full

1.0

INPUT REFERRED NOISE

VREF = 1.0 V

25°C

2.04

LSB rms

ANALOG INPUTS

Differential Input Voltage Range (Internal VREF = 1.0 V)

Full

1.46

2.06

V p-p

Common-Mode Voltage (VCM)

Full

2.05

Differential Input Capacitance1

Full

1.5

Analog Full Power Bandwidth

Full

GHz

POWER SUPPLY

AVDD1

Full

1.22

1.25

1.28

AVDD2

Full

2.44

2.50

2.56

AVDD3

Full

3.2

3.3

3.4

DVDD

Full

1.22

1.25

1.28

DRVDD

Full

1.22

1.25

1.28

SPIVDD

Full

1.22

1.8

3.4

IAVDD1

Full

464

503

IAVDD2

Full

396

455

IAVDD32

Full

100

IDVDD (Default SPI—NSR Mode)

Full

141

164

IDVDD (VDR Mode)

Full

117

138

IDRVDD3

Full

110

123

ISPIVDD

Full

POWER CONSUMPTION

Total Power Dissipation

Default SPI—NSR Mode3

Full

2.2

2.37

VDR Mode3

Full

2.16

2.34

Power-Down Dissipation

Full

0.71

Standby4

Full

1.4

1 Differential capacitance is measured between the VIN+x and VIN−x pins (x = A, B).

2 AVDD3 current changes based on the Buffer Control 1 setting (see Figure 46).

3 Parallel interleaved LVDS mode. The power dissipation on DRVDD changes with the output data mode used.

4 Standby can be controlled by the SPI.

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