AD6679 datasheet(41/81 Pages) AD

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Data Sheet

AD6679

Rev. B | Page 41 of 81

NCO

MIXER

(OPTIONAL)

DDC 3

SYNC

REAL/I

REAL/Q

REAL/I

CONVERTER 6

Q CONVERTER 7

NCO

MIXER

(OPTIONAL)

DDC 0

SYNC±

REAL/I

REAL/Q

REAL/I

CONVERTER 0

Q CONVERTER 1

NCO

MIXER

(OPTIONAL)

DDC 1

SYNC±

REAL/I

REAL/Q

REAL/I

CONVERTER 2

Q CONVERTER 3

NCO

MIXER

(OPTIONAL)

DDC 2

SYNC±

REAL/I

REAL/Q

REAL/I

CONVERTER 4

Q CONVERTER 5

ADC

SAMPLING

REAL/I

ADC

SAMPLING

REAL/I

SYNCHRONIZATION

CONTROL CIRCUITS

SYNC±

Figure 63. DDC Detailed Block Diagram

Figure 64 shows an example usage of one of the four DDC

blocks with a real input signal and four half-band filters (HB4 +

HB3 + HB2 + HB1). It shows both complex (decimate by 16)

and real (decimate by 8) output options.

When DDCs have different decimation ratios, the chip

decimation ratio (Register 0x201) must be set to the lowest

decimation ratio of all the DDC blocks. In this scenario,

samples of higher decimation ratio DDCs are repeated to match

the chip decimation ratio sample rate. Whenever the NCO

frequency is set or changed, the DDC soft reset must be issued.

If the DDC soft reset is not issued, the output may potentially

show amplitude variations.

Table 13 through Table 17 show the DDC samples when the

chip decimation ratio is set to 1, 2, 4, 8, or 16, respectively.

When DDCs have different decimation ratios, the chip decimation

ratio must be set to the lowest decimation ratio of all the DDC

channels. In this scenario, samples of higher decimation ratio

DDCs are repeated to match the chip decimation ratio sample

rate.

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