ISL70003ASEH datasheet(21/36 Pages) INTERSIL

21 / 36 page

ISL70003ASEH

FN8746.0

August 5, 2015

Submit Document Feedback

Functional Description

The ISL70003ASEH is a monolithic synchronous buck regulator

IC with integrated power MOSFETs. The device utilizes

voltage-mode control with feed-forward and switches at a

nominal frequency of 500kHz or 300kHz. It is fabricated on a

0.6μm BiCMOS junction isolated process optimized for power

management applications. With this device and a handful of

external components, a complete synchronous buck DC/DC

converter can be readily implemented. The converter accepts an

input voltage ranging from 3V to 13.2V and provides a tightly

regulated output voltage ranging from 0.6V to ~90% of the input

voltage at output currents ranging from 0A to 9A. Typical

applications include Point Of Load (POL) regulation for FPGAs,

CPLDs, DSPs, DDR memory and microprocessors.

Power Blocks

The power output stage of the regulator consists of ten power

blocks that are paralleled to provide full 9A output current

capability at TJ = +125°C. The block diagram in Figure 44 shows

a top level view of the individual power blocks.

SEL1 and SEL2 pins allow users to disable power blocks in order

to reduce switching losses in light load applications. Depending

on the state of these pins the ISL70003ASEH can operate with 2,

4, or 10 active power blocks and also be placed in a sleep mode.

Each power block has a power supply input pin, PVINx, a phase

output pin, LXx and a power supply ground pin, PGNDx. All PVINx

pins must be connected to a common power supply rail and all

PGNDx pins must be connected to a common ground. LXx pins

should be connected to the output inductor based on the

required load current and the state of the SEL1, SEL2 pins, but

must include the LX5 and LX6 pins. The unused LXx pins should

be left unconnected.

Scaled pilot devices associated with power blocks 5 and 6

provide current feedback for overcurrent detection and the IMON

current monitor feature. Power blocks 5 and 6 must be

connected to the output inductor at all times for proper

operation.

Initialization

The ISL70003ASEH initializes based on the state of the EN input

and POR input. Successful initialization prompts a soft-start

interval and the regulator begins slowly ramping the output

voltage. Once the commanded output voltage is within the

proper window of operation, the power-good signal changes state

from low to high indicating proper regulator operation.

Enable

The EN pin accepts TTL/CMOS logic input as described in the

Electrical Specifications” table on page 11. When the voltage on

the EN pin exceeds its logic rising threshold, the controller

monitors the POR voltage before initiating the soft-start function

for the PWM regulator. When EN is pulled low, the device enters

shutdown mode and the supply current drops to a typical value of

1.5mA. All internal power devices are held in a high impedance

state while in shutdown mode. Due to the internal 5V clamp, the

EN pin should be driven no higher than 5V or excessive leakage

current may be seen on the pin. In standalone applications the

FIGURE 42. OVERCURRENT RESPONSE

FIGURE 43. HICCUP RESPONSE IN OCP

Typical Performance Curves Unless otherwise noted, Test platform is the ISL70003ASEHEV1Z where V

IN = 12V,

VOUT = 3.3V, IOUT = 3A, fSW = 500kHz, CIN = 4x 100µF + 5x1µF, LOUT = 3.3µH, COUT = 1x 150µF + 1µF, TCASE = +25°C, All outputs active. (Continued)

OUTPUT VOLTAGE, 2V/DIV

INDUCTOR CURRENT, 5A/DIV

LXx VOLTAGE, 5V/DIV

PGOOD, 10V/DIV

OUTPUT VOLTAGE, 2V/DIV

INDUCTOR CURRENT, 10A/DIV

LXx VOLTAGE, 5V/DIV

SS VOLTAGE, 2V/DIV

POWER BLOCK 6

PGND6

POWER BLOCK 7

POWER BLOCK 8

POWER BLOCK 1

POWER BLOCK 2

POWER BLOCK 3

PVIN6

PGND7

PVIN7

PGND8

PVIN8

PGND1

PVIN1

PGND2

PVIN2

PGND3

PVIN3

LX2

LX1

LX3

LX6

LX7

LX8

POWER BLOCK 4

POWER BLOCK 9

POWER BLOCK 5

POWER BLOCK 10

PGND4

PVIN4

PGND5

PVIN5

LX5

LX4

PVIN9

PVIN10

LX9

LX10

FIGURE 44. POWER BLOCK DIAGRAM

PGND9

PGND10

and OCPA

OCPB and IMON

Note: Shaded blocks indicate pilot current and current sensors.

ISL70003ASEH bảng dữ liệu(PDF) 21 Page - Intersil Corporation

ISL70003ASEH bảng dữ liệu(HTML) 21 Page - Intersil Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

bảng dữ liệu tải về

Link URL