SC2440AEVB datasheet(10/28 Pages) SEMTECH

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General Description

SC2440A

The SC2440A is a dual constant frequency peak current-

mode step-down switching regulator with integrated 2A

high-side transistors. Both regulators share the same volt-

age reference, oscillator and synchronizing circuit. Turn-on

of the power transistors is phase-shifted by 80° for input

ripple reduction. The two regulators are otherwise identical,

independent and are capable of producing two indepen-

dent outputs from a common power supply.

The free-running frequency of the master oscillator is pro-

grammed with an external resistor from the ROSC pin to

ground, giving the user the flexibility of setting the switch-

ing frequency according to the input to output voltage

conversion ratio. The master clock is fed into a frequency

divider for phase clocks generation. As a result, each regula-

tor runs at half the master clock rate (Figure 2). The SC2440A

can also be synchronized to an external clock.

The SC2440A uses peak current-mode control. The inner

current loop of current-mode control reduces the double

reactive poles of the output LC filter to a single real pole,

easing loop compensation. A simple Type-2 compensation

network ensures stability with fast transient response.

The switch collector current of each channel is sensed with

an integrated sense resistor. The sensed current is summed

with a slope-compensating ramp before it is compared

with the error amplifier output. The PWM comparator trip

point determines the switch turn-on pulse width (Figure

2). ILIM is a cycle-by-cycle current-limit comparator that

turns off the power switch whenever the sensed-signal

exceeds 8mV.

Driving the base of the power transistor above the input

power supply rail minimizes the power transistor turn-on

voltage and maximizes efficiency. An external bootstrap

circuit (formed by the capacitor C

2 and the diode D3 in Fig-

ure ) generates a voltage higher than V

IN at the BST pin.

The bootstrapped voltage generated becomes the supply

voltage for the power transistor driver.

The SS pin is a multiple-function pin. An external capacitor

connected from the SS pin to ground together with the

internal charging and discharging circuits set the soft-start

and overload shutoff times for the regulator (Figure 3).

The SS pin can also be used to shut off the corresponding

regulator. When either SS pin is pulled below 0.8V, the cor-

responding regulator is turned off. If both SS pins are pulled

below 0.5V, then the SC2440A will undergo overall shut-

down, drawing less than 40μA from a 5V input. When either

SS pin is released, the corresponding soft-start capacitor is

charged with a .8μA current source (not shown in Figure 3).

When either SS voltage exceeds 0.35V, the internal regulator

in the SC2440A turns on. V

IN quiescent current increases to

4.mA. An internal fast charge circuit (not shown) quickly

charges the soft-start capacitor to V. At this juncture, the

fast charge circuit turns off and the .8μA current source

slowly charges the soft-start capacitor.

The error amplifier EA in Figure 2 has two non-inverting

inputs. The non-inverting input with the lower voltage pre-

dominates. One of the non-inverting inputs is biased to a

precision V reference and the other non-inverting input is

tied to the output of the amplifier A

. Amplifier A produces

an output V

= 2(VSS – .33) if VSS > .33V. For VSS < .33V,

= 0. During start up, COMP is pulled low initially. When

SS exceeds .2V, COMP is released. However the effective

non-inverting input of EA remains zero. As a result, the

regulator output stays at zero as the soft-start capacitor is

charged from .2V to .33V. The regulator output starts

to ramp when V

SS exceeds .33V and VCOMP rises above .V.

If the soft-start interval is made sufficiently long, then the

FB voltage (hence the output voltage) will track V

during

start up. V

SS must be at least .88V to ensure regulation.

Zener diode D

Z clamps COMP to a voltage higher than that

corresponding to the cycle-by-cycle switch current limit.

Current flow in D

Z indicates clamping of COMP.

As the load draws more current from the regulator, the

current-limit comparator ILIM (Figure 2) limits the switch

current on a cycle-by-cycle basis. If the over-current con-

dition persists, then the COMP voltage will continuously

increase to its clamp level, eventually setting the overload

shutdown latch X

3. The COMP pin is immediately pulled

low, turning off the corresponding regulator (Figure 3).

Overload shutdown can occur during soft-start. However

the SS capacitor is always charged to the upper trip volt-

age of the Schmitt trigger X

before it can be discharged.

The reset input of the discharge latch X

2 stays high before

the soft-start capacitor is charged to 2.V. Once the soft-

start capacitor is charged above 2.V, X

output goes high

and the reset input of the SS discharge latch X

2 goes low,

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