VS6955CA datasheet(49/90 Pages) STMICROELECTRONICS

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VS6955CA

Video data interface

The video stream output from the VS6955CA through the compact camera port (CCP) or

camera serial interface (CSI) contains both video data and other auxiliary information. This

section describes the frame formats.

The selection of the video data format is controlled using the following register:

CSI_SIGNALLING_MODE (0x0111)

0 - CCP2 data/clock

1 - CCP2 data/strobe

2 - CSI-2 (default)

Changing the video data format must be performed when the sensor is in software standby.

•

The VS6955CA supports maximum output data rate of 1.0 Gbps when operated in CSI-

2 single lane mode.

•

The VS6955CA CCP lane is capable of transmitting at 640 Mbps.

•

The CSI-2 data lane transmitter supports:

–

unidirectional master

–HS-TX

–

LP-TX (ULPS)

–

CIL-MUYN function

•

The CSI-2 clock lane transmitter supports:

–

unidirectional master

–HS-TX

–

LP-TX (ULPS)

–

CIL-MCNN function

6.1

Frame format

The frame format for the VS6955CA is described by the frame format description registers,

see Table 10 on page 25. For CCP2 this results in a frame as shown in Figure 10 and for

CSI-2 it results in a frame as shown in Figure 11.

Figure 10. VS6955CA CCP2 frame format

Interframe padding

Bayer pixel data

3 embedded data lines

Frame start code

Frame end code

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