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VS6955CA bảng dữ liệu(PDF) 13 Page - STMicroelectronics |
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VS6955CA bảng dữ liệu(HTML) 13 Page - STMicroelectronics |
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13 / 90 page ![]() DocID028071 Rev 2 13/90 VS6955CA Functional description 21 remain at LP-00. If this state is entered from streaming then the data pads go to LP-11 at the end of the current frame. The internal video timing is reset to the start of a video frame in preparation for the enabling of active video. The values of the serial interface registers such as exposure and gain are preserved. The system clock must remain active when communicating with the sensor. This state is entered by releasing the device from hard reset by writing 0x00 to the mode control register (0x0100) or commanding a soft reset by writing 0x01 to the software reset register (0x0103). Note: After a soft reset or the transition of XSHUTDOWN to high, all registers are returned to their default values. 3.1.4 Streaming The VS6955CA streams live video. This mode is entered by writing 0x01 to the mode control register (0x0100). 3.2 Power management 3.2.1 Power-up procedure The digital and analog supply voltages can be powered up in any order, for example, VDIG then VANA or VANA then VDIG. On power-up the on-chip power-on reset cell ensures that the CCI register values are initialized correctly to their default values. The EXTCLK clock can either be initially low and then enabled during software standby mode or EXTCLK can be a free running clock. The power-up sequence timing constraints are shown in Table 4. Table 4. Power-up sequence timing constraints Symbol Parameter Min. Max. Units t0 VANA rising – VDIG rising VANA and VDIG may rise in any order. The rising separation can vary from 0 ns to indefinite. ns t1 VDIG rising – VANA rising ns t2 VDIG / VANA rising – XSHUTDOWN rising XSHUTDOWN must rise later than or coincident with the later rising supply (VDIG or VANA) µs t3 XSHUTDOWN – First I2C transaction 28,500 EXTCLK cycles t4 Minimum number of EXTCLK cycles prior to the first I2C transaction 28,500 EXTCLK cycles t5 PLL start up/lock time - 1 ms t6 Entering streaming mode – First frame start sequence (fixed part) -10 ms t7 Entering streaming mode – First frame start sequence (variable part) = Integration time fine_integration_ time_min |
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