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STM32F479AI bảng dữ liệu(PDF) 142 Page - STMicroelectronics |
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STM32F479AI bảng dữ liệu(HTML) 142 Page - STMicroelectronics |
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142 / 208 page ![]() Electrical characteristics STM32F479xx 142/208 DocID028010 Rev 2 I2S interface characteristics Unless otherwise specified, the parameters given in Table 65 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.20 for more details on the input/output alternate function characteristics (CK, SD, WS). Note: Refer to the I2S section of RM0386 reference manual for more details on the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior, source clock precision might slightly change the values. The values of these parameters might be slightly impacted by the source clock precision. DCK depends mainly on the value of ODD bit. The digital Table 65. I2S dynamic characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK I2S Main clock output - 256x8K 256xFs(2) MHz fCK I2S clock frequency Master data - 64xFs Slave data - 64xFs DCK I2S clock frequency duty cycle Slave receiver 30 70 % tv(WS) WS valid time Master mode 0 5 ns th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 3.5 - Slave mode PCM short pulse mode(3) 3.5 - th(WS) WS hold time Slave mode 0.5 - Slave mode PCM short pulse mode(3) 1- tsu(SD_MR) Data input setup time Master receiver 5 - tsu(SD_SR) Slave receiver 1.5 - th(SD_MR) Data input hold time Master receiver 5 - th(SD_SR) Slave receiver 1.5 - tv(SD_ST) Data output valid time Slave transmitter (after enable edge) - 19 tv(SD_MT) Master transmitter (after enable edge) - 2.50 th(SD_ST) Data output hold time Slave transmitter (after enable edge) 5 - th(SD_MT) Master transmitter (after enable edge) 0 - 1. Guaranteed based on test during characterization. 2. 128xFs maximum is 24.756 MHz (APB1 Maximum frequency). 3. Measurement done with respect to I2S_CK rising edge. |
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