STM32F756VG datasheet(155/228 Pages) STMICROELECTRONICS

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STM32F756xx

Electrical characteristics

196

Figure 45. 12-bit buffered /non-buffered DAC

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly

without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

5.3.26

Communications interfaces

I2C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification and user

manual rev. 03 for:

•

Standard-mode (Sm): with a bit rate up to 100 kbit/s

•

Fast-mode (Fm): with a bit rate up to 400 kbit/s.

•

Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly

configured (refer to RM0385 reference manual) and when the I2CCLK frequency is greater

than the minimum shown in the table below:

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS

connected between the I/O pin and VDD is disabled, but is still present.

Table 74. Minimum I2CCLK frequency in all I2C modes

Symbol

Parameter

Condition

Min

Unit

f(I2CCLK)

I2CCLK

frequency

Standard-mode

MHz

Fast-mode

Analog Filtre ON

DNF=0

Analog Filtre OFF

DNF=1

Fast-mode Plus

Analog Filtre ON

DNF=0

22.5

Analog Filtre OFF

DNF=1

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