STM32F756VG datasheet(138/228 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F756xx

138/228

DocID027589 Rev 4

5.3.15

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the ANSI/ESDA/JEDEC JS-001-2012 and ANSI/ESD S5.3.1-2009 standards.

Static latchup

Two complementary static tests are required on six parts to assess the latchup

performance:

•

A supply overvoltage is applied to each power supply pin

•

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latchup standard.

5.3.16

I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or

above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product

operation. However, in order to give an indication of the robustness of the microcontroller in

cases when abnormal injection accidentally happens, susceptibility tests are performed on a

sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating input mode. While current is injected into

the I/O pin, one at a time, the device is checked for functional failures.

Table 53. ESD absolute maximum ratings

Symbol

Ratings

Conditions

Class

Maximum

value(1)

Unit

VESD(HBM)

Electrostatic discharge

voltage (human body model)

TA = +25 °C conforming to

ANSI/ESDA/JEDEC JS-001-2012

2000

VESD(CDM)

Electrostatic discharge

voltage (charge device model)

TA = +25 °C conforming to ANSI/ESD

S5.3.1-2009, LQFP100, LQFP144,

LQFP176, LQFP208, WLCSP143,

UFBGA176, TFBGA100 and TFBGA216

packages

250

1. Guaranteed by characterization results.

Table 54. Electrical sensitivities

Symbol

Parameter

Conditions

Class

Static latch-up class

TA = +105 °C conforming to JESD78A

II level A

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