STM32F756VG datasheet(131/228 Pages) STMICROELECTRONICS

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STM32F756xx

Electrical characteristics

196

Jitter(3)

Master I2S clock jitter

Cycle to cycle at

12.288 MHz on

48KHz period,

N=432, R=5

RMS

peak

±280

Average frequency of

12.288 MHz

N = 432, R = 5

on 1000 samples

-90

WS I2S clock jitter

Cycle to cycle at 48 KHz

on 1000 samples

-400

IDD(PLLI2S)(4)

PLLI2S power consumption on

VDD

VCO freq = 100 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

IDDA(PLLI2S)(4)

PLLI2S power consumption on

VDDA

VCO freq = 100 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Guaranteed by characterization results.

Table 44. PLLI2S characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 45. PLLISAI characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fPLLSAI_IN

PLLSAI input clock(1)

-0.95(2)

12.10

MHz

fPLLSAIP_OUT

PLLSAI multiplier output clock

for 48 MHz

fPLLSAIQ_OUT

PLLSAI multiplier output clock

for SAI

216

fPLLSAIR_OUT

PLLSAI multiplier output clock

for LCD-TFT

216

fVCO_OUT

PLLSAI VCO output

100

432

tLOCK

PLLSAI lock time

VCO freq = 100 MHz

200

µs

VCO freq = 432 MHz

100

300

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