STM32F303VE datasheet(156/184 Pages) STMICROELECTRONICS

156 / 184 page

Electrical characteristics

STM32F303xD STM32F303xE

156/184

DocID026415 Rev 4

Figure 52. 12-bit buffered /non-buffered DAC

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external

loads directly without the use of an external operational amplifier. The buffer can be bypassed by

configuring the BOFFx bit in the DAC_CR register.

6.3.21

Comparator characteristics

Update rate(3)

Max frequency for a correct

DAC_OUT change when

small variation in the input

code (from code i to i+1LSB)

CLOAD

≤50 pF,

RLOAD

≥ 5 kΩ

MS/s

tWAKEUP(3)

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

CLOAD

≤50 pF,

RLOAD

≥ 5 kΩ

-6.5

µs

PSRR+ (1)

Power supply rejection ratio

(to VDDA) (static DC

measurement

CLOAD

= 50 pF,

No RLOAD

≥ 5 kΩ,

–67

–40

1. Guaranteed by design, not tested in production.

2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is

involved.

3. Data based on characterization results, not tested in production.

Table 85. DAC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 86. Comparator characteristics(1)

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

VDDA

Analog supply voltage

3.6

VIN

Comparator input voltage

range

-0

VDDA

VBG

Scaler input voltage

VREFINIT

VSC

Scaler offset voltage

±5

±10

tS_SC

Scaler startup time from

power down

0.2

STM32F303VE bảng dữ liệu(PDF) 156 Page - STMicroelectronics

STM32F303VE bảng dữ liệu(HTML) 156 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL