C164CL datasheet(64/79 Pages) INFINEON

64 / 79 page

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

ALE fall. edge to RdCS,

WrCS (no RW delay)

t43 CC -4 + tA

–

-4

–

Address float after RdCS,

WrCS (with RW delay)

t44 CC –

–

0ns

Address float after RdCS,

WrCS (no RW delay)

t45 CC –

–

TCL

RdCS to Valid Data In

(with RW delay)

t46 SR –

16 +

–

2TCL - 24

RdCS to Valid Data In

(no RW delay)

t47 SR –

36 +

–

3TCL - 24

RdCS, WrCS Low Time

(with RW delay)

t48 CC 30 + tC

–

2TCL - 10

–

RdCS, WrCS Low Time

(no RW delay)

t49 CC 50 + tC

–

3TCL - 10

–

Data valid to WrCS

t50 CC 26 + tC

–

2TCL - 14

–

Data hold after RdCS

t51 SR 0

–

Data float after RdCS

t52 SR –

20 +

–

2TCL - 20

Address hold after

RdCS, WrCS

t54 CC 20 + tF

–

2TCL - 20

–

Data hold after WrCS

t56 CC 20 + tF

–

2TCL - 20

–

1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Multiplexed Bus (cont’d)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2

tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

C164CL bảng dữ liệu(PDF) 64 Page - Infineon Technologies AG

C164CL bảng dữ liệu(HTML) 64 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

bảng dữ liệu tải về

Link URL