ST2100 datasheet(11/39 Pages) STMICROELECTRONICS

11 / 39 page

DocID025777 Rev 1

11/39

ST2100

Architecture description

3.3

Memory subsystem

The multiport memory controller within the memory subsystem manages DDR mobile up to

166 MHz and DDR2 up to 333 MHz external memory. Internally, it handles 5 ports

supporting all the chip master ports.

The multiport memory controller block has a programmable arbitration scheme and the

transactions happen on a different layer from the main bus. It also offers a local FIFO to

increase the throughput and reduce the latency.

3.4

Expi subsystem



PCI Express Gen1 (PCI Express standard version 1.1) single lane X1 dual mode

–

Root Complex mode is supported.

–

Endpoint mode is supported.



Serial ATA compliant with SATA/150 specifications



PHY is standard 8-bit/16-bit PIPE PHY interface

3.5

Basic subsystem



8 FIFOs and 16 high performance DMA channels with two AHB interfaces to parallelize

the activity when two channels are working at the same time.



48 Kbytes of ROM (for boot procedure)



“Serial Memory Interface” (SMI) supporting external serial Flash.



Color LCD controller (CLCD) up to 1024 x 768 resolution at 24 bpp (true color)

supporting STN/TFT display panels



Three pair of 16 bit general purpose timers with programmable prescaler



Watchdog timer



RTC with separate power supply allowing battery connection



Up to 104 “Multi-Function” I/Os (MFIOs) multiplexed with peripheral I/Os:

–

Allows a large number of possible application scenarios

–

Up to 40 GPIOs with interrupt capability



System controller, reset and clock generation, and miscellaneous registers array

allowing a full configurability of the system.

ST2100 bảng dữ liệu(PDF) 11 Page - STMicroelectronics

ST2100 bảng dữ liệu(HTML) 11 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

bảng dữ liệu tải về

Link URL