M95040-DRDW3TP datasheet(26/41 Pages) STMICROELECTRONICS

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Application design recommendations

M95040-A125 M95040-A145

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DocID024225 Rev 6

5.1.3

Power-down

During power-down (continuous decrease in the VCC supply voltage below the minimum

VCC operating voltage defined in Table 12 and Table 13), the device must be:

•

deselected (Chip Select (S) should be allowed to follow the voltage applied on VCC),

•

in Standby power mode (there should not be any internal Write cycle in progress).

5.2

Implementing devices on SPI bus

Figure 16 shows an example of three devices, connected to the SPI bus master. Only one

device is selected at a time, so that only the selected device drives the Serial Data output

(Q) line. All the other devices outputs are then in high impedance.

Figure 16. Bus master and memory devices on the SPI bus

1. The Write Protect (W) and Hold (HOLD) signals must be driven high or low as appropriate.

A pull-up resistor connected on each /S input (represented in Figure 16) ensures that each

device is not selected if the bus master leaves the /S line in the high impedance state.

5.3

Error Correction Code (ECC x 1)

The Error Correction Code (ECC x 1) is an internal logic function which is transparent for the

SPI communication protocol.

The ECC x 1 logic is implemented on each byte of the memory array. If a single bit out of the

byte happens to be erroneous during a Read operation, the ECC x 1 detects this bit and

replaces it with the correct value. The read reliability is therefore much improved.

M95040-DRDW3TP bảng dữ liệu(PDF) 26 Page - STMicroelectronics