L7292D datasheet(44/60 Pages) STMICROELECTRONICS

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Buck regulator description

L7292

44/60

DocID028601 Rev 1

Figure 16. Soft-start example

11.5

PWM mode

In the PWM operative mode, the output voltage is regulated using a quasi constant on-time

control in conjunction with a modulated ramp signal which reproduces the output voltage

ripple in order to achieve loop stability and to be unaffected by the external capacitor ESR

value.

The OTA output generates a voltage proportional to the difference between the reference

voltage and Vout in order to minimize the DC error on Vout.

The ramp output is compared with VOUT to trigger the Ton event. The duration of Ton is

managed by a FLL that controls dynamically the on-time duration so that the PSR can

achieve a relatively constant switching frequency. The advantage of the constant frequency

is to minimize the EMI and to give the possibility to add a fixed filter to remove residual

noise. In addition a slew rate programmability of the switching output is implemented.

L7292D bảng dữ liệu(PDF) 44 Page - STMicroelectronics