USB3500 datasheet(30/45 Pages) MICROCHIP

30 / 45 page

USB3500

DS00002103A-page 30

 2005 - 2016 Microchip Technology Inc.

6.9

HS Detection Handshake – HS Downstream Facing Port

Upon entering the HS Detection process (T0), XCVRSELECT and TERMSELECT are in FS mode. The DP pull-up is

asserted and the HS terminations are disabled. The Link then sets OPMODE to Disable Bit Stuffing and NRZI encoding,

XCVRSELECT to HS mode, and begins the transmission of all 0's data, which asserts a HS K (chirp) on the bus (T1).

The device chirp must last at least 1.0ms, and must end no later than 7.0ms after HS Reset T0. At time T1 the device

begins listening for a chirp sequence from the downstream facing port. If the downstream facing port is HS capable,

then it will begin generating an alternating sequence of Chirp K’s and Chirp J’s (T3) after the termination of the chirp

from the device (T2). After the device sees the valid chirp sequence Chirp K-J-K-J-K-J (T6), it will enter HS mode by

setting TERMSELECT to HS mode (T7).

Figure 6-4 provides a state diagram for Chirp K-J-K-J-K-J validation. Prior to the end of reset (T9) the device port must

terminate the sequence of Chirp K’s and Chirp J’s (T8) and assert SE0 (T8-T9). Note that the sequence of Chirp K’s

and Chirp J’s constitutes bus activity.

TABLE 6-7:

HS DETECTION HANDSHAKE TIMING VALUES (FS MODE)

Timing

Parameter

Description

Value

HS Handshake begins. DP pull-up enabled, HS

terminations disabled.

0 (reference)

Device enables HS Transceiver and asserts Chirp K

on the bus.

T0 < T1 < HS Reset T0 + 6.0ms

Device removes Chirp K from the bus. 1ms

minimum width.

T1 + 1.0 ms < T2 <

HS Reset T0 + 7.0ms

Earliest time when downstream facing port may

assert Chirp KJ sequence on the bus.

T2 < T3 < T2+100µs

Chirp not detected by the device. Device reverts to

FS default state and waits for end of reset.

T2 + 1.0ms < T4 <

T2 + 2.5ms

Earliest time at which host port may end reset

HS Reset T0 + 10ms

Note:

• T0 may occur to 4ms after HS Reset T0.

• The Link must assert the Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration.

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