USB2250I datasheet(14/43 Pages) MICROCHIP

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 2009 - 2015 Microchip Technology Inc.

DS00002005A-page 14

USB2250/50i/51/51i

Memory

Address Bus

MA16

O12

These signals address memory locations within

the external memory.

MA[15:2]

107

113

111

109

106

108

110

112

114

116

O12

These signals address memory locations within

the external memory.

MA[1:0] /

CLK_

SEL[1:0]

O12

MA[1:0]: These signals address memory

locations within the external memory.

I/O12PD

CLK_SEL[1:0]: During RESET_N assertion,

these pins will select the operating frequency of

the external clock, and the corresponding weak

pull-down resistors are enabled.

When RESET_N is negated, the value on these

pins will be latched internally and these pins will

revert to MA[1:0] functionality; the internal pull-

downs will be disabled.

CLK_SEL[1:0] = '00'. 24 MHz

CLK_SEL[1:0] = '01'. RESERVED

CLK_SEL[1:0] = '10'. RESERVED

CLK_SEL[1:0] = '11'. 48 MHz

If the latched value is '1', the corresponding MA

pin is tri-stated when the chip is in power down

state.

If the latched value is '0', the corresponding MA

pin will function identically to MA[15:3] pins at all

times (other than during RESET_N assertion).

Memory Write

Strobe

nMWR

O12

This pin is the active low program Memory Write

strobe signal.

Memory Read

Strobe

nMRD

115

O12

This pin is the active low program Memory Read

strobe signal.

Memory Chip

Enable

nMCE

O12

This pin is the active low program Memory Chip

Enable strobe signal.

This signal is asserted when any external

access is being done by the processor.

This signal is held to the logic 'high' while

RESET_N is asserted.

TABLE 5-1:

USB2250/50I/51/51I 128-PIN VTQFP PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

128-Pin

VTQFP

Buffer

Type

Description

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