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LAN9730 bảng dữ liệu(PDF) 138 Page - Microchip Technology |
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LAN9730 bảng dữ liệu(HTML) 138 Page - Microchip Technology |
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138 / 222 page ![]() LAN9730/LAN9730i DS00001946A-page 138 2012-2015 Microchip Technology Inc. 0 Flow Control on Any Frame (FCANY) When this bit is set, the device will assert back pressure or transmit a pause frame when the AFC level is reached and any frame is received. Setting this bit enables full-duplex flow control when the device is operating in full-duplex mode. When this mode is enabled during half-duplex operation, the flow controller does not decode the MAC address and will send a pause frame upon receipt of a valid preamble (i.e., immediately at the beginning of the next frame after the RX Data FIFO level is reached). When this mode is enabled during full-duplex operation, the flow controller will immediately instruct the MAC to send a pause frame when the RX Data FIFO level is reached. The MAC will queue the pause frame transmission for the next available window. Setting this bit overrides bits [3:1] of this register. R/W 0b Bits Description Type Default |
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