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LMP92066PWPR bảng dữ liệu(PDF) 21 Page - Texas Instruments

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tên linh kiện LMP92066PWPR
Giải thích chi tiết về linh kiện  Dual Temperature-Controlled DAC
PDF  63 Pages
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nhà sản xuất  TI1 [Texas Instruments]
Trang chủ  http://www.ti.com
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LMP92066PWPR bảng dữ liệu(HTML) 21 Page - Texas Instruments

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DACx Input Code
0V
-5V
VDDB
VSSB
0xFFF
0x000
A=-1
DACx Input Code
5V
0V
VDDB
VSSB
0xFFF
A=1
0x000
LMP92066
www.ti.com
SNAS634B – MARCH 2014 – REVISED JANUARY 2016
When the span is above GNDA, or VDDB = 5 V and VSSB = 0 V, then the output buffer gain is A = 1. The net
effect on the output of the analog processing chain is shown in Figure 28. The DAC input codes in the range of
0x000 to 0xFFF are mapped to the output voltage in the range of 0 V to 5 V.
Figure 28. Output of Analog Processing Chain: Net Effect
If the span is below GNDA, or VDDB = 0 V and VSSB = –5 V, then the output buffer gain is A = –1. This
configuration is depicted Figure 29. This results in effective mapping of the DAC input codes in the range of
0x000 to 0xFFF, to the output voltage range of 0 V to –5 V.
Figure 29. Common Mode Voltage Below GNDA,
or VDDB = 0 V and VSSB = –5 V
NOTE
Both Buffer Amplifiers share the VDDB and VSSB rails. Therefore, both Buffers produce
gain of A = 1, or both produce gain of A = –1.
The state of the VDDB and VSSB supplies, whether their span is above or below GNDA is indicated by the state
of the DRV_STATUS.GAN bit, and can be read by the controller via the I2C interface.
Copyright © 2014–2016, Texas Instruments Incorporated
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