DLPC3433ZVB datasheet(34/62 Pages) TI1

34 / 62 page

DLPC3433, DLPC3438

DLPS035B – FEBRUARY 2014 – REVISED JANUARY 2016

www.ti.com

Table 7. DLPC343x Compatible SPI Flash Device Options(1) (2)

DVT(3)

DENSITY (Mb)

VENDOR

PART NUMBER

PACKAGE SIZE

1.8-V COMPATIBLE DEVICES

Yes

4 Mb

Winbond

W25Q40BWUXIG

2 × 3 mm USON

Yes

4 Mb

Macronix

MX25U4033EBAI-12G

1.43 × 1.94 mm WLCSP

Yes

8 Mb

Macronix

MX25U8033EBAI-12G

1.68 × 1.99 mm WLCSP

2.5- OR 3.3-V COMPATIBLE DEVICES

Yes

16 Mb

Winbond

W25Q16CLZPIG

5 × 6 mm WSON

(1)

The flash supply voltage must match VCC_FLSH on the DLPC343x. Special attention needs to be paid when ordering devices to be

sure the desired supply voltage is attained as multiple voltage options are often available under the same base part number.

(2)

Beware when considering Numonyx (Micron) serial flash devices as they typically do not have the 4KB sector size needed to be

DLPC343x compatible.

(3)

All of these flash devices appear compatible with the DLPC343x, but only those marked with yes in the DVT column have been

validated on the EVM3430 reference design. Those marked with no can be used at the ODM’s own risk.

8.3.3 Serial Flash Programming

Note that the flash can be programmed through the DLPC343x over I2C or by driving the SPI pins of the flash

directly while the DLPC343x I/O are tri-stated. SPI0_CLK, SPI0_DOUT, and SPI0_CSZ0 I/O can be tri-stated by

holding RESETZ in a logic low state while power is applied to the DLPC343x. Note that SPI0_CSZ1 is not tri-

stated by this same action.

8.3.4 SPI Signal Routing

The DLPC343x is designed to support two SPI slave devices on the SPI0 interface, specifically, a serial flash

and the DLPA200x. This requires routing associated SPI signals to two locations while attempting to operate up

to 36 MHz. Take special care to ensure that reflections do not compromise signal integrity. To this end, the

following recommendations are provided:

•

The SPI0_CLK PCB signal trace from the DLPC343x source to each slave device should be split into

separate routes as close to the DLPC343x as possible. In addition, the SPI0_CLK trace length to each device

should be equal in total length.

•

The SPI0_DOUT PCB signal trace from the DLPC343x source to each slave device should be split into

separate routes as close to the DLPC343x as possible. In addition, the SPI0_DOUT trace length to each

device should be equal in total length(use the same strategy as SPI0_CLK).

•

The SPI0_DIN PCB signal trace from each slave device to the point where they intersect on their way back to

the DLPC343x should be made equal in length and as short as possible. They should then share a common

trace back to the DLPC343x.

•

SPI0_CSZ0 and SPI0_CSZ1 need no special treatment because they are dedicated signals which drive only

one device.

8.3.5 I2C Interface Performance

Both DLPC343x I2C interface ports support 100-kHz baud rate. By definition, I2C transactions operate at the

speed of the slowest device on the bus, thus there is no requirement to match the speed grade of all devices in

the system.

8.3.6 Content-Adaptive Illumination Control

Content-adaptive illumination control (CAIC) is an image processing algorithm that takes advantage of the fact

that in common real-world image content most pixels in the images are well below full scale for the for the R, G,

and B digital channels being input to the DLPC343x. As a result of this the average picture level (APL) for the

overall image is also well below full scale, and the system’s dynamic range for the collective set of pixel values is

not fully utilized. CAIC takes advantage of this headroom between the source image APL and the top of the

available dynamic range of the display system.

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