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DLPC3433ZVB bảng dữ liệu(PDF) 29 Page - Texas Instruments

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DLPC3433ZVB bảng dữ liệu(HTML) 29 Page - Texas Instruments

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Input
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DLPC3433, DLPC3438
www.ti.com
DLPS035B – FEBRUARY 2014 – REVISED JANUARY 2016
7.2 Input Source
Table 3. Supported Input Source Ranges(1)(2)(3)(4)
SOURCE RESOLUTION RANGE
FRAME RATE
INTERFACE
BITS / PIXEL (5)
IMAGE TYPE
RANGE
HORIZONTAL
VERTICAL
Parallel
24 max
2D only
320 to 1280
200 to 800
4.75 to 94.00 Hz (6)
Parallel
24 max
3D only
320 to 1280
200 to 720
94.00 to 122.4 Hz
BT.656-NTSC (7)
(8)
2D only
720
240
60 ±3 Hz
BT.656-PAL (7)
(8)
2D only
720
288
50 ±3 Hz
(1)
The user must stay within specifications for all source interface parameters such as max clock rate and max line rate.
(2)
The max DMD size for all rows in the table is 854 × 480.
(3)
To achieve the ranges stated, the composer-created firmware used must be defined to support the source parameters used.
(4)
These interfaces are supported with the DMD sequencer sync mode command (3Bh) set to auto.
(5)
Bits / Pixel does not necessarily equal the number of data pins used on the DLPC343x. Fewer pins are used if multiple clocks are used
per pixel transfer.
(6)
Frame rates below 10.00 Hz have not been tested by TI.
(7)
All parameters in this row follow the BT.656 standard.
(8)
BT.656 uses 16-bit 4:2:2 YCr/Cb.
7.2.1 Parallel Interface Supports Six Data Transfer Formats
•
24-bit RGB888 or 24-bit YCrCb888 on a 24 data wire interface
•
18-bit RGB666 or 18-bit YCrCb666 on a 18 data wire interface
•
16-bit RGB565 or 16-bit YCrCb565 on a 16 data wire interface
•
16-bit YCrCb 4:2:2 (standard sampling assumed to be Y0Cb0, Y1Cr0, Y2Cb2, Y3Cr2, Y4Cb4, Y5Cr4, …)
•
8-bit RGB888 or 8-bit YCrCb888 serial (1 color per clock input; 3 clocks per displayed pixel)
–
On an 8 wire interface
•
8-bit YCrCb 4:2:2 serial (1 color per clock input; 2 clocks per displayed pixel)
–
On an 8 wire interface
PDATA Bus – Parallel Interface Bit Mapping Modes shows the required PDATA(23:0) bus mapping for these six
data transfer formats.
7.2.1.1 PDATA Bus – Parallel Interface Bit Mapping Modes
Figure 11. RGB-888 / YCrCb-888 I/O Mapping
Figure 12. RGB-666 / YCrCb-666 I/O Mapping
Copyright © 2014–2016, Texas Instruments Incorporated
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