DLPC3433CZVB datasheet(47/62 Pages) TI1

47 / 62 page

VSS

VDD

VSS_

PLLD

VDD_

PLLD

VSS

VSS_

PLLM

Signal

VSS

VDD

PLL_

REF

CLK_I

Signal

VDD_

PLLM

Signal

VSS

VIA to Common Analog

Digital Board Power Plane

VIA to Common Analog

Digital Board Ground Plane

ASIC Pad

PCB Pad

Local

Decoupling

for the PLL

Digital Supply

Signal VIA

Signal

PLL_

REF

CLK_O

Crystal Circuit

1.1 V

PWR

GND

DLPC3433, DLPC3438

www.ti.com

DLPS035B – FEBRUARY 2014 – REVISED JANUARY 2016

11 Layout

11.1 Layout Guidelines

11.1.1 PCB Layout Guidelines for Internal ASIC PLL Power

The following guidelines are recommended to achieve desired ASIC performance relative to the internal PLL.

The DLPC343x contains 2 internal PLLs which have dedicated analog supplies (VDD_PLLM , VSS_PLLM,

VDD_PLLD, VSS_PLLD). As a minimum, VDD_PLLx power and VSS_PLLx ground pins should be isolated using

a simple passive filter consisting of two series Ferrites and two shunt capacitors (to widen the spectrum of noise

absorption). It’s recommended that one capacitor be a 0.1uf capacitor and the other be a 0.01uf capacitor. All

four components should be placed as close to the ASIC as possible but it’s especially important to keep the

leads of the high frequency capacitors as short as possible. Note that both capacitors should be connected

across VDD_PLLM and VSS_PLLM / VDD_PLLD and VSS_PLLD respectfully on the ASIC side of the Ferrites.

For the ferrite beads used, their respective characteristics should be as follows:

•

DC resistance less than 0.40

•

Impedance at 10 MHz equal to or greater than 180

•

Impedance at 100 MHz equal to or greater than 600

The PCB layout is critical to PLL performance. It is vital that the quiet ground and power are treated like analog

signals. Therefore, VDD_PLLM and VDD_PLLD must be a single trace from the DLPC343x to both capacitors

and then through the series ferrites to the power source. The power and ground traces should be as short as

possible, parallel to each other, and as close as possible to each other.

Figure 25. PLL Filter Layout

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