DLPC910 datasheet(32/50 Pages) TI1

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DLPC910

DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

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7.5.1.2 MAIN_STATUS Register

The MAIN_STATUS register is used for reading the status of the DLPC910. The register can be polled during

operation to obtain the current state of the DLPC910.

Table 9. MAIN_STATUS Register

ADDRESS

BITS

DESCRIPTION

RESET

TYPE

DMD initialization in progress flag

0 - No DMD initialization activity

0x0

1 - DMD initialization in progress

DMD initialization in progress flag 1

0 - No DMD stage 1 initialization activity

0x0

1 - DMD stage 1 initialization activity in progress

DMD initialization in progress flag 2

0 - No DMD stage 2 initialization activity

0x0

1 - DMD stage 2 initialization activity in progress

DMD supports AB channels

0 - Operation of DMD AB buses not enabled

0x0

1 - Operation of DMD AB buses enabled

DMD supports CD channels

0 - Operation of DMD CD buses not enabled

0x0

1 - Operation of DMD CD buses enabled

Input interface calibration in progress

0 - Input interface calibration inactive

0x0

1 - Input interface calibration in progress

0x000C

DVALID alignment on interface A ok

0 - DVALID alignment invalid on channel A

0x0

1 - DVALID alignment correct on channel A

DVALID alignment on interface B ok

0 - DVALID alignment invalid on channel B

0x0

1 - DVALID alignment correct on channel B

DVALID alignment on interface C ok

0 - DVALID alignment invalid on channel C

0x0

1 - DVALID alignment correct on channel C

DVALID alignment on interface D ok

0 - DVALID alignment invalid on channel D

0x0

1 - DVALID alignment correct on channel D

System PLL locked flag

0 - PLL not locked

0x0

1 - PLL locked

Reference PLL locked flag

0 - PLL not locked

0x0

1 - PLL locked

31:12:00

UNUSED

0x0

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