CDCL1810

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SLLS781D – FEBRUARY 2007 – REVISED NOVEMBER 2014

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Added Note 1 to the Function Block Diagram ...................................................................................................................... 10

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Added the SDA/SCL Connections Recommendations section ............................................................................................ 12

6 Device Comparison Table

PACKAGED DEVICES

FEATURES

–40°C to +85°C

CDCL1810RGZT

48-pin VQFN (RGZ) Package, small tape and reel

–40°C to +85°C

CDCL1810RGZR

48-pin VQFN (RGZ) Package, tape and reel

Table 2. Device Feature Comparison

FEATURE

CDCL1810

CDCL1810A

Divider Synchronization after power up and after each programming

Yes

No

access. During Synchronization all outputs Yes No are disabled.

Output Group Phase Adjustment

Yes

No

Device Revision ID

b'011'

b'100'

1:10 Clock Fanout

Yes

Yes

Outputs grouped into two divider banks

Yes

Yes

Individual Output enabled/disable with I2C

Yes

Yes

Continuous and independent operation of outputs which are not

programmed, while configuring and programming No Yes other

No

Yes

outputs.

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