LINP

/FAULT

AVCC

RINP

RINN

AGND

GAIN

LIMRATE

SSCTRL

LINN

/SD

GVDD

LIMTHRES

1SPW

TPA3144D2

www.ti.com

SLOS907B – APRIL 2015 – REVISED JULY 2015

Feature Description (continued)

Figure 16. GAIN Pin Voltage Programming by GVDD Resistor Divider

The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside

are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance

from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.

The selected input gain is latched at device start up and cannot be changed when SD is high.

For design purposes, the input network (discussed in the next section) should be designed assuming an input

impedance of 7.2 k

Ω, which is the absolute minimum input impedance of the TPA3144D2. At the lower gain

settings, the input impedance could increase as high as 72 k

Ω.

Table 1. Gain Setting

AMPLIFIER GAIN (dB)

INPUT IMPEDANCE (k

Ω)

GAIN PIN VOLTAGE

TYP

TYP

0 V (GND)

20

60

2.3 V (1/3·GVDD)

26

30

4.6 V (2/3·GVDD)

32

15

6.9 V (GVDD)

36

9

9.3.2

SD Operation

minimum level during periods of nonuse for power conservation. The SD input pin should be held high (see

specification table for trip point) during normal operation when the amplifier is in use. Pulling SD low causes the

outputs to mute and the amplifier to enter a low-current state. Never leave SD unconnected, because amplifier

operation would be unpredictable.

For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power

supply voltage.

9.3.3 Gain Limit Control, LIMTHRES and LIMRATE

The TPA3144D2 has built-in gain limiters with two operation modes for load and system protection: Voltage

limiting and temperature limiting. The voltage limiting mode controls the TPA3144D2 voltage gain to limit the

output signal without signal clipping, and the temperature control mode limits the device power dissipation to

keep the die temperature within recommended operating conditions. Both voltage limiter and thermal limiter

attack and release speeds (time per 0.5dB gain step) are controlled by the LIMRATE pin:

Copyright © 2015, Texas Instruments Incorporated

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